Abstract: Aiming at the drawback of static software Huffman coding which has large computational complexity and the problem of dynamic Huffman coding that makes the decoder more complicated,a quasi-dynamic hardware Huffman encoder was designed.This encoder encodes an array of data statically,then outputs the result parallelly which guarantees that it has a high encoding speed,and its dalay time is only the total time of an encoding process.First,for taking advantage of parallelism of hardware,static and dynamic sorting network are both implemented to meet different encoding demands.Then,a hardware binary tree building unit and a resolving unit driven by data flow are implemented to get the final Huffman codes.Finally,the Huffman codes are outputted based on data stored in FIFO.The design results illustrate that,this quasi-dynamic based on Nexys4 platform shows advantages of high working frequency (over 100MHz),high throughput,low latency and can simplify the design of decoder.

Key words: Huffman coding,Hardware sorting,Hardware binary tree,Field-programmable gate array(FPGA),First in first out(FIFO)