计算机科学 ›› 2014, Vol. 41 ›› Issue (5): 55-58.doi: 10.11896/j.issn.1002-137X.2014.05.012

• 2013容错计算 • 上一篇    下一篇

用不同敏化方法提高超速测试的故障覆盖率

魏建龙,邝继顺   

  1. 湖南大学信息科学与工程学院 长沙410082;湖南大学信息科学与工程学院 长沙410082
  • 出版日期:2018-11-14 发布日期:2018-11-14
  • 基金资助:
    本文受国家自然科学基金项目(60673085,60773207)资助

Improving Fault Coverage by Adopting Different Sensitization Criterion for Faster Than At-Speed Testing

WEI Jian-long and KUANG Ji-shun   

  • Online:2018-11-14 Published:2018-11-14

摘要: 面向小时延缺陷(small delay detect,SDDs)的测试产生方法不仅要求测试产生算法复杂度低,还要尽可能地检测到小时延缺陷。超速测试避免了因测试最长敏化通路而带来的测试效率过低的问题,而且它要求测试向量按敏化通路时延进行分组,对每组分配一个合适的超速测试频率,再采用一种可快速、准确选择特定长度的路径选择方法来有效地提高测试质量。同时,文中首次通过优先选用单通路敏化标准对短通路进行检测,对关键通路有选择地进行非强健测试,相对采用单一的敏化方法,能以很小的时间代价提高含有小时延缺陷的结点的跳变时延故障覆盖率(TDF)。在ISCAS’89基准电路中对小时延缺陷的检测结果表明:用不同敏化方法进行测试产生,能 在低的cpu时间里取得更高的跳变时延故障覆盖率。

Abstract: Test generation method for the small delay defects (SDDs) not only requires low algorithm complexity,but also more possibility to detect small delay.Faster than at-speed testing avoids to detect the longest sensitization paths for poor efficiency.It requires test patterns to be delicately classified into groups according to the delay of sensitization paths,and each group is managed to be applied at certain clock frequency.Then it adopts a path selection method to identify a certain length of paths quickly and accurately,which can achieve high test quality.At the same time,the paper firstly proposed that choosing single path sensitization criterion for short paths and nonrobust sensitization criterion for the critical paths to test can improve transition delay fault coverage (TDF) of the nodes which contain small delay defects at the cost of a little of time compared with adopting single sensitization criterion.Experimental results on ISCAS’89benchmark circuits show that the proposed method can achieve higher transition delay fault coverage of SDDs with low CPU time.

[1] Breuer M A.The effect of races,delays and delay faults on testgeneration[J].IEEE Transactions on Computers,1974,22(10):1078-1092
[2] http://www.itrs.net/Links/2008ITRS/Home2008.htm
[3] Qiu W,Wang J,Walker D M H,et al.K longest paths per gate(KLPG) test generation for scan-based sequential circuits[C]∥Proc.Int.Test Conf.(ITC).2004:223-231
[4] Sato Y,Hamada S,Maeda T,et al.Invisible delay quality-SDQLmodel lights up what could not be seen[C]∥Proc.Int.Test Conf.(ITC).2005:47
[5] Kajihara S,Morishima S,Takuma A,et al.A framework of high-quality transition fault ATPG for scan circuits[C]∥Proc.Int.Test Conf.(ITC).2006
[6] Shao Y,Pomeranz I,Reddy S M.On generating high qualitytests for transition faults[C]∥Proc.Asian Test Symp(ATS).2002:1-8
[7] Lin X,Tsai K,Wang C,et al.Timing-aware ATPG for highquality at-speed testing of small delay defects[C]∥Proc.Asian Test Symp.(ATS).2006:139-146
[8] 王杰,李华伟,梁华国.针对小时延缺陷的时延测试方法综述[C]∥第十三届全国容错计算学术会议.2009:383-390
[9] Lee B N,Wang L C,Abadir M S.Reducing pattern delay variations for screening frequency dependent defects[C]∥Proc.VLSI Test Symp.(VTS).2005:153-160
[10] Ahmed N,Tehranipoor M.A novel faster-than-at-speed transition-delay test method considering IR-drop effects[J].IEEE Trans.Comput.-Aided Design(CAD) Integr.Circuits Syst.,2009,28(10):1573-1582
[11] Fu Xiang,Li Hua-wei,Li Xiao-wei.Testable Path Selection and Grouping for Faster Than At-Speed Testing[J].IEEE Trans.on VLSI Systems,2012,0(2):236-247
[12] Fujiwara H,Shimono T.On the Acceleration of Test Pattern Algorithms[J].IEEE Transactions on Computers,1983,32(12):1137-1144
[13] Kajihara S,Morishima S,Takuma A,et al.A framework of high-quality transition fault ATPG for scan circuits,[C]∥Procee-dings IEEE of International Test Conference(ITC).2006:2

No related articles found!
Viewed
Full text


Abstract

Cited

  Shared   
  Discussed   
No Suggested Reading articles found!