Computer Science ›› 2017, Vol. 44 ›› Issue (Z11): 33-38.doi: 10.11896/j.issn.1002-137X.2017.11A.006
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OUYANG Cheng-tian, CHEN Li-li and WANG Xi
[1] ECKSTEIN A A P,MICHIGAN.Jack Kilby [J].IEEE Annals of the History of Computing,2007,29(1):90-95. [2] MOORE G E.Cramming more components onto integrated circuits [J].Electronics,1965,38(8):114-117. [3] Executive Interview:Bill Bottoms Talks about Revamping the ITRS Roadmap.http://www.3dincites.com/2015/03/executive-interview-bill-bottoms-talks-revamping-itrs-roadmap. [4] CONSTANTINESCU C.Trends and challenges in VLSI circuit reliability [J].IEEE Micro.,2003,23(4):14-19. [5] NEUMANN J V.Probabilistic logics and the synthesis of reliable organisms from unreliable components [M]∥ Shannon C,ed.Automata Studies.Princeton:Princeton University Press,1956:43-98. [6] CHUNG W K.Topics in reliability of sequential circuits [D]:Ottawa:University of Ottawa,1970. [7] MARAIS P D.Reliability Analysis of sequential circuits [D].Ottawa:University of Ottawa,1972. [8] MARAIS P D,KRIEGER M.Reliability Analysis of Logic Circuits [J].IEEE Transactions on Reliability,1975,24(1):46-52. [9] CHEN I N.Analysis and reliability estimation for probabilistic switching circuits [J].IEEE Transactions on Reliability,1971,20(1):36-38. [10] GLINSKI G S,CHUNG W K.A markov model for the reliability of probabilistic sequential circuits with bernoulli inputs [C]∥Proceedings of 6th Annual Allerton Conference on Circuit and System Theory.Urbana,Illinois:Illinois University Press,1968:568-577. [11] ZIEGLER J F,CURTIS H W,MUHLFELD H P,et al.IBM experiments in soft fails in computer electronics (1978-1994) [J].IBM Journal of Research and Development,1996,40(1):3-18. [12] MAY T C,WOODS M H.Alpha-particle-induced soft errors in dynamic memories [J].IEEE Transactions on Electron Devices,1979,26(1):2-9. [13] ASADI H,TAHOORI M B.Soft error modeling and protection for sequential elements [C]∥Proceedings of 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.Monterey,USA:IEEE Computer Society,2005:463-471. [14] FAZELI M,MIREMADI S G,ASADI H,et al.A fast analytical approach to multi-cycle soft Error rate estimation of sequential circuits [C]∥Proceedings of 13th Euromicro Conference on Digital System Design:Architectures,Methods and Tools.Lille,France:IEEE Computer Society,2010:797-800. [15] HOLCOMB D,WENCHAO L,SESHIA S A.Design as you see FIT:System-level soft error analysis of sequential circuits [C]∥Proceedings of Design,Automation & Test in Europe Con-ference & Exhibition.Nice,France:IEEE Computer Society,2009:785-790. [16] JAHANIRAD H,MOHAMMADI K,ATTARSHARGHI P.Sequential circuits reliability analysis using conditional probabi-lities [C]∥Proceedings of 19th Iranian Conference on Electrical Engineering(ICEE).Tehran,Iran:IEEE Computer Society,2011:1-4. [17] JAHANIRAD H,MOHAMMADI K,ATTARSHARGHI P.Sequential circuits reliability analysis using conditional probabi-lities [C]∥2011 19th Iranian Conference on Proceedings of Electrical Engineering (ICEE).2011:1-4. [18] LINGASUBRAMANIAN K,BHANJA S.Probabilistic errormodeling for sequential logic [C]∥Proceedings of 7th IEEE Conference on Nanotechnology.Hong Kong:IEEE Computer Society,2007:616-620. [19] LINGASUBRAMANIAN K,BHANJA S.An error model tostudy the behavior of transient errors in sequential circuits [C]∥Proceedings of 22nd International Conference on VLSI Design.New Delhi,India:IEEE Computer Society,2009:485-490. [20] MAHDAVI S J S,MOHAMMADI K.SCRAP:Sequential circuits reliability analysis program [J].Microelectronics Reliability,2009,49(7):924-933. [21] MISKOV-ZIVANOV N,MARCULESCU D.Soft error rateanalysis for sequential circuits [C]∥Proceedings of Design,Automation & Test in Europe Conference & Exhibition.Nice,France:IEEE Computer Society,2007:1-6. [22] MISKOV-ZIVANOV N,MARCULESCU D.Modeling and Optimization for Soft-Error Reliability of Sequential Circuits [J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2008,27(5):803-816. [23] MOHAMMADI K,JAHANIRAD H,ATTARSHARGHI P.Fast Reliability Analysis Method for Sequential Logic Circuits [C]∥2011 21st International Conference on Proceedings of Systems Engineering (ICSEng).2011:352-356. [24] 欧阳城添,江建慧.基于概率转移矩阵的时序电路可靠度计算方法[J].电子学报,2013,41(1):171-177. [25] ZHU D,LI T,LI S K.An Approximate Soft Error Reliability Sorting Approach Based on State Analysis of Sequential Circuits [C]∥2010 IEEE 25th International Symposium on Proceedings of Defect and Fault Tolerance in VLSI Systems (DFT).2010:209-217. [26] CHA H,RUDNICK E M,CHOI G S,et al.A fast and accurate gate-level transient fault simulation environment [C]∥Procee-dings of 23th International Symposium on Fault-Tolerant Computing.Toulouse,France:IEEE Computer Society,1993:310-319. [27] MING Z,SHANBHAG N R.Soft-Error-Rate-Analysis (SERA) Methodology [J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2006,25(10):2140-2155. [28] FISHMAN G.Monte carlo:concepts,algorithms and applications[M]∥Operations Research.New York:Springer-Verlag,1995. [29] CHOUDHURY M R,MOHANRAM K.Accurate and scalable reliability analysis of logic circuits [C]∥Proceedings of IEEE/ACM Conference on Design,Automation & Test in Europe Conference & Exhibition,2007(DATE’07).2007:1-6. [30] FLAUQER J T,DAVEAU J M,NAVINER L,et al.Fast reliability analysis of combinatorial logic circuits using conditional probabilities [J].Microelectronics Reliability,2010,50(9-11):1215-1218. [31] KRISHNASWAMY S,VIAMONTES G F,MARKOV I L,et al.Accurate reliability evaluation and enhancement via probabilistic transfer matrices [C]∥Proceedings of IEEE/ACM Conference on Design,Automation and Test in Europe.Orlando,USA:IEEE Computer Society,2005:282-287. [32] 王真,江建慧,员春欣.高性能处理器的差错校正技术[J].计算机研究与发展,2008,45(2):358-366. [33] 肖杰,江建慧,等.一种基于迭代PTM模型的电路可靠性评估方法[J].计算机学报,2014(7):1508-1520. [34] 肖杰,江建慧,等.面向晶体管级广义门电路的PTM可靠性计算 [J].中国科学:信息科学,2014(10):1226-1238. [35] 欧阳城添,江建慧,等.触发器可靠度计算的F-PTM方法[J].电子学报,2016(9):2219-2226. [36] 黄海林,唐志敏,许彤.龙芯1 号处理器的故障注入方法与软差错敏感性分析[J].计算机研究与发展,2007,3(10):1820-1827. [37] MUKHERJEE S S,WEAVER C,EMER J,et al.A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor [C]∥Proceedings of 36th Annual IEEE/ACM International Symposium on Microarchitecture.San Diego,CA,USA:IEEE Computer Society,2003:29-40. [38] KRISHNASWAMY S,PLAZA S M,MARKOV I L,et al.Signature-Based SER Analysis and Design of Logic Circuits[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2009,28(1):74-86. [39] 胡谋.计算机容错技术[M].北京:中国铁道出版社,1995. [40] 徐拾义.可信计算系统设计和分析[M].北京:清华大学出版社,2006. [41] GeNIe & SMILE.http://genie.sis.pitt.edu.2010. [42] 王真,江建慧.基于概率转移矩阵的串行电路可靠度计算方法[J].电子学报,2009,37(2):241-247. |
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