Computer Science ›› 2018, Vol. 45 ›› Issue (2): 249-253.doi: 10.11896/j.issn.1002-137X.2018.02.043

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Optimization Method of Low Power Test Vectors Based on Hamming Sorting for X Bits Padding

TAN En-min and FAN Yu-xiang   

  • Online:2018-02-15 Published:2018-11-13

Abstract: The test power consumption in the process of integrated circuit testing is usually much higher than the normal power consumption of the integrated circuit.However,the high test power consumption may cause the circuit to be damaged or the chip to be burned.An optimization method of low power test vectors based on Hamming sorting for X bits padding was proposed to reduce the test power consumption.Firstly,the test vectors in the test set are ranged from high X bits to low X bits.Then,the test vectors are sorted in ascending order according to the Hamming distance.Finally,the test power consumption is reduced by padding X bits for the sorted test set reasonably,which increases the correlation between test vectors.The ISCAS’85 standard circuit was used as the test object.The experimental results show that compared with using the non-optimized test set,the test power consumption is reduced obviously with the optimized test set.

Key words: Test vector,Hamming distance,X bits,Low power design

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