基于FPGA的ZUC高性能数据加密方案

doi:10.11896/jsjkx.221100070

计算机科学 ›› 2023, Vol. 50 ›› Issue (11): 374-382.doi: 10.11896/jsjkx.221100070

• 信息安全 • 上一篇

基于FPGA的ZUC高性能数据加密方案

张博林^1,2, 李斌^1,2, 燕云飞¹, 魏源鑫¹, 周清雷¹

1 郑州大学计算机与人工智能学院郑州 450001
2 河南省网络密码技术重点实验室郑州 450001

收稿日期:2022-11-09 修回日期:2023-03-29 出版日期:2023-11-15 发布日期:2023-11-06
通讯作者: 李斌(iebinli@zzu.edu.cn)
作者简介:(421049800@qq.com)
基金资助:
河南省网络密码技术重点实验室研究课题(LNCT2022-A14);国家重点研发计划(2018XXXXXXX01);河南省科技攻关(232102211055)

ZUC High Performance Data Encryption Scheme Based on FPGA

ZHANG Bolin^1,2, LI Bin^1,2, YAN Yunfei¹, WEI Yuanxin¹, ZHOU Qinglei¹

1 Country School of Computer and Artificial Intelligence,Zhengzhou University,Zhengzhou 450001,China
2 Henan Key Laboratory of Network Cryptography Technology,Zhengzhou 450001,China

Received:2022-11-09 Revised:2023-03-29 Online:2023-11-15 Published:2023-11-06
About author:ZHANG Bolin,born in 1999,master.His main research interests include high-performance computing and information security.LI Bin,born in 1986,Ph.D,lecturer.His main research interests include high-performance computing and information security.
Supported by:
Henan Key Laboratory of Network Cryptography Technology(LNCT2022-A14) ,National Key R & D Program of China(2018XXXXXXX01) and Key Scientific and Technological Project of Henan Province(232102211055).

摘要/Abstract

摘要： 祖冲之(ZUC)算法是我国自主研制的流密码算法,现已被3GPP LTE采用为第四代移动通信加密标准。为适应大数据时代对于国产密码性能的高要求,设计了一套以祖冲之算法为核心的高性能数据加密方案。该方案中包含两种不同结构形式的加密算法核心,分别针对短报文和长报文两种不同的应用情形,基于FPGA平台,采用CLA和CSA加法器设计了半流水线和全流水线形式的ZUC流密码电路结构,以改进的ZUC加密模式,配合高速内存通信和多iv并行加密,实现了高性能加密方案,极大提高了加解密效率。该方案工作时,可使用控制模块来配置加密算法。实验结果表明,与其他方案相比,所提方案的算核工作频率分别提高了40.8%~209.5%和62.1%~445.4%,数据吞吐率达到了25.728 Gb/s和46.08 Gb/s,适用于边缘设备、车联网数据加密等高性能加密场景。

关键词: 祖冲之算法, 现场可编程门阵列, 高性能加密, 硬件实现, 流水线

Abstract: ZUC algorithm is a stream cipher algorithm independently developed by China,which has been adopted as the fourth generation mobile communication encryption standard by 3GPP LTE.In order to meet the high requirements of the big data era for the performance of domestic passwords,a set of high-performance data encryption scheme with ZUC algorithm as the core is designed.The scheme includes two encryption algorithm cores of different structure forms.Aiming at two different application situations of short message and long message respectively,based on the FPGA platform,the semi-pipelined and full-pipelined ZUC stream cipher circuit structures are designed by using CLA and CSA adders.With the improved ZUC encryption mode,combined with high-speed memory communication and multi iv parallel encryption,the high-performance encryption scheme is realized,which greatly improves the encryption and decryption efficiency.When the scheme works,the encryption algorithm can be configured using the control module.Experimental results show that,compared with other schemes,the working frequency of the proposed algorithmis increased by 40.8%~209.5% and 62.1%~445.4% respectively,and the data throughput reaches 25.728 Gb/s and 46.08 Gb/s,meeting the high-performance encryption scenarios such as edge devices and Internet of Vehicles data encryption.

Key words: ZUC algorithm, FPGA, High performance encryption, Hardware implementation, Pipelined

中图分类号:

TP309

张博林, 李斌, 燕云飞, 魏源鑫, 周清雷. 基于FPGA的ZUC高性能数据加密方案[J]. 计算机科学, 2023, 50(11): 374-382. https://doi.org/10.11896/jsjkx.221100070

ZHANG Bolin, LI Bin, YAN Yunfei, WEI Yuanxin, ZHOU Qinglei. ZUC High Performance Data Encryption Scheme Based on FPGA[J]. Computer Science, 2023, 50(11): 374-382. https://doi.org/10.11896/jsjkx.221100070

参考文献

[1]WANG C,HOU Z K,LIU P C,et al.Security frequency hopping communication system based on improved ZUC algorithm[J].Journal of Tsinghua University(Natural Science Edition),2019,59(2):154-161.
[2]LIU Z,ZHANG L,JING J,et al.Efficient pipelined stream cipher ZUC algorithm in FPGA[C]//First Int’l Workshop on ZUC Algorithm,China.2010.
[3]KITSOS P,SKLAVOS N,SKODRAS A N.An FPGA imple-mentation of the ZUC stream cipher[C]//2011 14th Euromicro Conference on Digital System Design.IEEE,2011:814-817.
[4]ZHANG L,XIA L,LIU Z,et al.Evaluating the Optimized Implementations of SNOW3G and ZUC on FPGA[C]//2012 IEEE 11th International Conference on Trust,Security and Privacy in Computing and Communications.IEEE,2012:436-442.
[5]GUO H J,DONG X Z,GAO X W.Hardware Implementation of ZUC Algorithm Based on FPGA[J].Computer Engineering,2014,40(8):268-272.
[6]LIU Z,ZHANG Q,MA C,et al.HPAZ:A high-throughputpipeline architecture of ZUC in hardware[C]//2016 Design,Automation & Test in Europe Conference & Exhibition(DATE).IEEE,2016:269-272.
[7]LU B,YAN L M.Hardware architecture of an area optimized ZUC algorithm[J].Journal of Fudan University(Natural Science),2021,60(4):492-498,509.
[8]ZHOU W,WANG B,PAN W T.ZUC hardware implementation research[J].Foreign Electronic Measurement Technology,2015(7):66-71.
[9]ZHANG Y P,GAO Y,YAN Y,et al.Fast Software Implementation of ZUC Algorithm[J].Journal of Cryptologic Research,2021,8(3):388-401.
[10]BAI L,JIA W Y,ZHU G Z.Lightweight Hardware Design and Implementations of ZUC-256 Stream Cipher on FPGA[J].Journal of Cryptologic Research,2021,8(3):521-536.
[11]GB/T 33133.1-2016.2016-10-13,信息安全技术祖冲之序列密码算法第1部分:算法描述[S].国家密码管理局.2016.
[12]LI M,CUI Y J,NI Z Y,et al.Lightweight Hardware Design and Implementations of ZUC-256 Stream Cipher on FPGA[J].Journal of Data Acquisition & Processing,2022,37(3):695-702.
[13]GB/T 33133.2-2021.2021-10-11,信息安全技术祖冲之序列密码算法第2部分:保密性算法[S].全国信息安全标准化技术委员会(SAC/TC 260).2021.
[14]MATH S S,MANJULA R B,MANVI S S,et al.Data transactions on system-on-chip bus using AXI4 protocol[C]//2011 International Conference on Recent Advancements in Electrical,Electronics and Control Engineering.IEEE,2011:423-427.
[15]NOAMI A,PRADEEP KUMAR B,CHANDRASEKHAR P.High performance AXI4 interface protocol for multi-core memory controller on SoC[M]//Data Engineering and Communication Technology.Springer,Singapore,2021:131-140.
[16]ZHANG L,XIA L,LIU Z,et al.Evaluating the Optimized Implementations of SNOW3G and ZUC on FPGA[C]//Procee-dings of the 2012 IEEE 11th International Conference on Trust,Security and Privacy in Computing and Communications.2012:436-442.
[17]JINPENG W,TENG Z,BO Z,et al.An Innovative FPGA Implementations of the Secure frequency hopping communication system based on the improved ZUC algorithm[J].IEEE Access,2022,10:54634-54648.
[18]WANG Y,WU L,ZHANG X,et al.A hardware implementation of ZUC-256 stream cipher[C]//2020 IEEE 14th International Conference on Anti-counterfeiting,Security,and Identification(ASID).IEEE,2020:94-97.
[19]MUNDHE P,VERMA S,VENKATESAN S.A comprehensive survey on authentication and privacy-preserving schemes in VANETs[J].Computer Science Review,2021,41:100411.
[20]WANG Z Y,GUO Y,LI S Q,et al.Design of efficient anonymous identity authentication protocol for lightweight IoT devices[J].Journal on Communications,2022,43(7):49-61.

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基于FPGA的ZUC高性能数据加密方案

ZUC High Performance Data Encryption Scheme Based on FPGA

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