计算机科学 ›› 2017, Vol. 44 ›› Issue (Z11): 476-479.doi: 10.11896/j.issn.1002-137X.2017.11A.101

• 综合、交叉与应用 • 上一篇    下一篇

基于不同排序方法的快速霍夫曼编码硬件实现

李宜珂,王旃   

  1. 浙江大学电气工程学院 杭州310007,浙江大学电气工程学院 杭州310007
  • 出版日期:2018-12-01 发布日期:2018-12-01

Hardware Implementation of Fast Huffman Coding Based on Different Sorting Methods

LI Yi-ke and WANG Zhan   

  • Online:2018-12-01 Published:2018-12-01

摘要: 针对软件霍夫曼静态编码计算量大,而动态霍夫曼编码使得解码器同样复杂的缺点,提出了一种准动态霍夫曼硬件编码器。该编码器每次对一组数据序列进行静态编码,然后将编码并行输出,从而使得编码器具有较高的编码速度,而其延迟时间仅为一次编码过程的总时间。首先,为了充分利用硬件并行特性,分别使用动态排序和静态排序两种排序网络,以适应不同场合的编码需要。然后,使用数据流驱动的硬件二叉树构建和解析结构得到信源符号对应的霍夫曼编码。最后,将储存在FIFO中的输入数据查表并输出。设计结果表明,当使用Nexys4 DDR平台时,该编码器可以工作于100MHz以上的频率,同时具有吞吐高、延迟低、编码效率高和译码器简单的特性。

关键词: 霍夫曼编码,硬件排序,硬件二叉树,现场可编程门阵列,先入先出

Abstract: Aiming at the drawback of static software Huffman coding which has large computational complexity and the problem of dynamic Huffman coding that makes the decoder more complicated,a quasi-dynamic hardware Huffman encoder was designed.This encoder encodes an array of data statically,then outputs the result parallelly which guarantees that it has a high encoding speed,and its dalay time is only the total time of an encoding process.First,for taking advantage of parallelism of hardware,static and dynamic sorting network are both implemented to meet different encoding demands.Then,a hardware binary tree building unit and a resolving unit driven by data flow are implemented to get the final Huffman codes.Finally,the Huffman codes are outputted based on data stored in FIFO.The design results illustrate that,this quasi-dynamic based on Nexys4 platform shows advantages of high working frequency (over 100MHz),high throughput,low latency and can simplify the design of decoder.

Key words: Huffman coding,Hardware sorting,Hardware binary tree,Field-programmable gate array(FPGA),First in first out(FIFO)

[1] WANG G Y,ZHANG H S,LU M Y.Transformed HCT for parallel Huffman decoding [J].International Journal of Circuit Theory and Application,2015,3(11):1759-1774.
[2] LAWRENCE L,DANIEL H.A Fast Algorithm for OptimalLength-Limited Huffman Codes[J].Journal of the ACM(JACM),1990,7(3):464-473.
[3] LIU L Y,WANG J F,LEE,et al.Design and hardware architectures for dynamic Huffman coding [J].IEE Proceedings:Computers and Digital Techniques,1995,2(6):411-418.
[4] 张新超.基于FPGA的Huffman编码并行实现及高速存储系统设计[D].西安:长安大学,2015.
[5] 郭诚欣,陈红,孙辉,等.基于现代硬件的并行内存排序方法综述[J].计算机学报,2017,0(9):2070-2092.
[6] BATCHER K E.Sorting networks and their applications [C]∥AFIPS ’68.1968:307-314.
[7] 高劲松,孟令奎.硬件排序器研究进展[J].电子计算机与外部设备,1997(5):38-40.
[8] KOCH D,TORRESEN J.FPGASort:A high performance sorting architecture exploiting run-time reconfiguration on FPGAs for large problem sorting [C]∥Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays.2011:45-54.
[9] 倪泽峰,王振华,谭毅华,等.并行哈夫曼编码器的硬件设计与实现[J].微电子学与计算机,2002,9(10):66-68.
[10] HE T,XLI T,LI Y J,et al.The Analysis and Improvement of Huffman Algorithm[C]∥Proceedings of 2011 4th IEEE International Conference on Computer Science and Information Technology(ICCSIT 2011).2011:529-532.
[11] TAEYEON L,JAEHONG P.Design and implementation forstatic Huffman encoding hardware with parallel shifting algorithm[C]∥IEEE Nuclear Science Symposium Conference Record.2003:1315-1318.

No related articles found!
Viewed
Full text


Abstract

Cited

  Shared   
  Discussed   
No Suggested Reading articles found!