计算机科学

计算机科学 ›› 2026, Vol. 53 ›› Issue (6): 128-136.doi: 10.11896/jsjkx.250600137

• 高性能计算 • 上一篇    下一篇

基于 RISC-V 指令拓展的神经网络加速器编译技术研究

王一品1, 蔡成欢1, 许嘉滨2, 周学功3, 张逢喆3, 曹伟3, 张帆3, 余新胜4   

  1. 1 复旦大学软件学院 上海 200433
    2 复旦大学计算机科学技术学院 上海 200433
    3 复旦大学大数据研究院 上海 200433
    4 中国电子科技集团公司第三十二研究所 上海 201899
  • 收稿日期:2025-06-20 修回日期:2025-09-26 出版日期:2026-06-15 发布日期:2026-06-09
  • 通讯作者: 周学功(zhouxg@fudan.edu.cn)
  • 作者简介:(wyp000803@163.com)
  • 基金资助:
    国家重点研发计划(2022YFB4500903)

Study on Compilation Technology of Neural Network Accelerator Based on RISC-V InstructionExtension

WANG Yipin1, CAI Chenghuan1, XU Jiabin2, ZHOU Xuegong3, ZHANG Fengzhe3, CAO Wei3, ZHANG Fan3, YU Xinsheng4   

  1. 1 School of Software Engineering,Fudan University,Shanghai 200433,China
    2 School of Computer Science and Technology,Fudan University,Shanghai 200433,China
    3 Institute of Big Data,Fudan University,Shanghai 200433,China
    4 The 32nd Research Institute,China Electronics Technology Group Corporation (CETC),Shanghai 201899,China
  • Received:2025-06-20 Revised:2025-09-26 Published:2026-06-15 Online:2026-06-09
  • About author:WANG Yipin,born in 2000,postgra-duate.His main research interest is domain-specific hardware-software co-design.
    ZHOU Xuegong,Ph.D,assistant resear-cher.His main research interests include mimic intelligent computing,reconfigurable computing and EDA algorithms.
  • Supported by:
    National Key R & D Program of China(2022YFB4500903).

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摘要： 随着人工智能的快速发展,基于 RISC-V 指令扩展的神经网络加速器成为研究热点。深度学习编译器是实现神经网络模型在硬件平台上高效部署的关键。然而,结合硬件特性修改现有编译器的调优规则对开发人员要求较高,同时现有编译器缺乏对专门转置硬件单元的编译支持,无法通过数据流重构实现高效转置,导致未充分发挥此类硬件的性能潜力。针对这些问题,首先,基于 MLIR 框架设计了一款面向 RISC-V 神经网络专用加速器的编译工具链,可实现模型端到端的部署;其次,在 MLIR 框架中引入了硬件特征相关的 Dialect,编译器能够结合加速器缓冲区大小、脉动阵列尺寸、双缓冲策略以及数据流模式优化分块矩阵乘法操作,并结合硬件结构,通过改变矩阵数据流的方式实现矩阵转置操作,避免大规模数据的交换。此外,还根据脉动阵列特性实现了卷积算子融合以及矩阵乘法与向量计算的算子融合。实验结果表明,转置优化后运行速度平均提升了14.55倍,算子融合后运行速度平均提升了 41.59%,综合优化后 BERT 模型运行速度平均提升了 5.13%。

关键词: 深度学习编译器, RISC-V, 加速器, MLIR, 编译优化

Abstract: With the rapid advancement of artificial intelligence,RISC-V instruction set extended neural network accelerators have become a research hotspot.Deep learning compilers are critical for efficiently deploying neural network models on hardware platforms.However,modifying the tuning rules of existing compilers based on hardware characteristics places extremely high demands on developers.At the same time,existing compilers lack compilation support for specialized transposition hardware units and cannot achieve efficient transposition through data flow reconstruction,resulting in the performance potential of such hardware not being fully utilized.To address these issues,this paper first designs an MLIR-based compiler toolchain targeting RISC-V neural network accelerators,enabling end-to-end model deployment.Secondly,it introduces hardware-specific dialects within the MLIR framework.This allows the compiler to optimize tiled matrix multiplication by integrating accelerator buffer size,systolic array dimensions,double buffering strategies,and dataflow patterns.Furthermore,it implements efficient matrix transposition by adjusting data flow patterns according to the hardware architecture,eliminating the need for large-scale data exchange.The paper also implements convolution operator fusion and matrix multiplication-vector computation fusion based on systolic array features.Experimental results demonstrate an average speedup of 14.55× after transposition optimization,an average 41.59% speedup after operator fusion,and a comprehensive average speedup of 5.13% for BERT model execution.

Key words: Deep learning compiler, RISC-V, Accelerator, MLIR, Compilation optimization

中图分类号: 

  • TP314
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