计算机科学 ›› 2026, Vol. 53 ›› Issue (6A): 250300124-7.doi: 10.11896/jsjkx.250300124
孙安东, 张清毅
SUN Andong, ZHANG Qingyi
摘要： 近年来,基于RISC-V指令集的处理器,越来越受到学术界和产业界的重视。在处理器的微架构中,用于处理跳转指令的分支预测器影响着处理器的性能。对于流水线架构的处理器,高预测准确度的分支预测器,可以减少流水线冲刷的发生,进而缩短指令执行的时间。分支预测器通常依托饱和计数器进行预测,饱和计数器的状态转移与结果判定方式直接影响分支预测器的准确度。为使分支预测器可以捕捉并结合程序的变化趋势实现对跳转指令的处理,从而进一步提高其性能,基于对RISC-V指令集中跳转指令以及传统分支预测器工作机理的研究,通过优化饱和计数器的工作机制,在竞争分支预测器的基础上设计并实现了趋势分支预测器,并对其进行了实验验证。验证结果表明,趋势分支预测器相较于竞争分支预测器的预测准确度提高了19.26%,指令吞吐量提高了2.12%;相较于静态分支预测器的预测准确度提高了53.85%,指令吞吐量提高了9.6%。同时,趋势分支预测器有更大的硬件开销,在预测功能上相较于竞争分支预测器提高了约40.83%,相较于静态分支预测器提高了1 220%;在预测结果验证功能上的硬件开销,相较于竞争分支预测器提高了0.826%,相较于静态分支预测器提高了10.95%。
中图分类号:
| [1] LIU X L,LIN H Y,LIU P.A Review of RISC-V Instruction Set Architecture and Its Applications [J].China Integrated Circuit,2025,34(3):16-20,49. [2] LIU C,LIU M Y,ZHANG Y Q,et al.Design of a Motion Sensing Device Based on RISC-V Processor [J].Modern Information Technology,2025,9(3):32-36. [3] JING C X,LIU J,LI H K,et al.NA-ROB:Improvements Based on RISC-V Superscalar Processors [J].Application Research of Computers,2025,42(2):519-522. [4] TSIRAMUA S,MELADZE H,DAVITASHVILI T,et al.Structural Analysis of Multi-Core Processor and Reliability Evaluation Model[J].Mathematics,2025,13(3):515. [5] QIU P F,SUN R H,WANG C L,et al.Discovery and Exploitation of Low-Power Vulnerabilities in Modern Processors [J].Science China:Information Sciences,2025,55(2):297-325. [6] ZHU H Y,ZHOU Y L,LIU H J,et al.Research and Design of a Four-STage Pipeline Stack Processor [J].Computer Engineering and Design,2025,46(1):265-273. [7] JIN Z,DI H,HU T,et al.Real-Time Optimization of RISC-V Processors Based on Branch Prediction and Division Datab Dependency[J].Applied Sciences,2025,15(2):632. [8] ARRIBAS J M,HELLÍN M A,MATEO P M,et al.Design and implementation ofa synchronous Hardware Performance Monitor for a RISC-V space-oriented processor[J].Microprocessors and Microsystems,2025,112:105132. [9] DONG R,CUI B,SUN Y,et al.A combined side-channel and transient execution attack scheme on RISC-V processors[J].Computers & Security,2025,150:104297. [10] ZHU K,HE X B,TENG Q Q.Research on Register Allocation Based on RISC-V Architecture [J].Intelligent Computers and Applications,2025,15(5):61-67. [11] RICARDO N,DAVID C,LLUÍS T.RisCO2:Implementationand Performance Evaluation of RI SC-V Processors for Low-Power CO2 Concen tration Sensing[J].Micromachines,2023,14(7). [12] ZHONG D Y,ZENG Q L,ZHOU J K,et al.Design and Implementation of a Hardware-Software Co-Verification Platform Based on RISC-V Processor [J].Information Technology and Informatization,2024(11):23-26. [13] Esperanto and NEC Cooperate on Initiative to Advance Next-Next RISC-VChips and Software Solutions for HPC[J].Wireless News,2024. [14] ZOU X,PENG Y,LI T,et al.Seesaw:A 4096-bit vector processor for accelerating Kyber based on RISC-V ISA extensions[J].Parallel Computing,2025,123:103121. [15] CORA G,SIO D C,AZIMI S,et al.Selective hardening ofRISCV soft-processors for space applications[J].Microelectronics Reliability,2025,167:115667. [16] DEMYANA E,MOHAMMED H,GIHAN N.Development an efficient AXI-interconnect unit between set of customized peripheral devices and an implemented dual-core RISC-V processor[J].The Journal of Supercomputing,2023,79(15):17000-17019. [17] GALLEGO F A,ARRIBAS J M,RÍO D G I,et al.Count overflow and privilege mode filtering extension implementation on a RISC-V on-board processor[J].Microprocessors and Microsystems,2024,109:105084. [18] BUSH S.Microchip opts for 64-bit with Risc-V[J].Electronics Weekly,2024,(2863):7. [19] CHOI E,PARK J,LEE K,et al.Day-Night architecture:Development of an ultra-low power RISC-V processor for wearable anomaly detection[J].Journal of Systems Architecture,2024,152:103161. [20] Anonymous.Quad core RiscV board based on Eswin processor[J].Electronics Weekly,2024(2857):9. [21] VOLOKITIN V D,VASILIEV E P,KOZINOV E A,et al.Improved Vectorization of OpenCV Algorithms for RISC-V CPUs[J].Lobachevskii Journal of Mathematics,2024,45(1):130-142. [22] EBRAHIMIAZANDARYANI F,FEY D.ExTern:BoostingRISC-V core performance using ternary encoding[J].Microprocessors and Microsystems,2024,107:105058. [23] SU A,ZHANG J,YANG J.Implementation and performance comparison of MMC firmware on RISC-V and ARM-based MCUs[J].Journal of Instrumentation,2024,19(4). [24] LI H,JING C,LIU J.Performance-Optimised Design of theRISC-V Five-STage Pipelined Processor NRP[J].International Journal of Advanced Computer Science and Applications(IJACSA),2024,15(2). [25] WANG H,LI D,ISSHIKI T.A Low-Power ReconfigurableDNN Accelerator for Instruction-Extended RISC-V:[J].IPSJ Transactions on System and LSI Design Methodology,2024,17(17):55-66. [26] SENTHILMURUGAN S,GUNASEELAN K.PerformanceAnalysis of Multicore Processor Using FOFO-Based Approximate Compatible ALU[J].Journal of Circuits,Systems and Computers,2023,33(4). [27] LIU J F,GAO W R,LIANG H Z,et al.Towards a universal and portable assembly code size reduction:a case study of RISC-V ISA[J].CCF Transactions on High Performance Computing,2024,6(3):263-273. [28] WEI Y,YANG Z J,TIE B,et al.Multi-level Dynamic Branch Predictor Based on Hummingbird E203 [J].Computer Engineering & Science,2024,46(5):785-793. [29] CHOI E,PARK J,LEE K,et al.Day-Night architecture:Development of an ultra-low power RISC-V processor for wearable anomaly detection[J].Journal of Systems Architecture,2024,152:103161. [30] YU S,SHI C F.Design of a Pedestrian Positioning SoC System Based on RISC-V Architecture [J].Journal of Terahertz Science and Electronic Information Technology,2024,22(9):959-966. |
|
||
首页