计算机科学

计算机科学 ›› 2023, Vol. 50 ›› Issue (11A): 220800045-7.doi: 10.11896/jsjkx.220800045

• 计算机软件&体系架构 • 上一篇    下一篇

面向边缘计算的轻量级网络硬件加速设计

余运俊1, 张鹏飞1, 龚汉城2, 陈敏2   

  1. 1 南昌大学信息工程学院 南昌 330000
    2 江西江投数字经济研究院 南昌 330000
  • 发布日期:2023-11-09
  • 通讯作者: 余运俊(yuyunjun@ncu.edu.cn)
  • 基金资助:
    国家国际科技合作专项(2014DFG72240);江西省重点研发计划项目(20214BBG74006)

Lightweight Network Hardware Acceleration Design for Edge Computing

YU Yunjun1, ZHANG Pengfei1, GONG Hancheng2, CHEN Min2   

  1. 1 School of Information Engineering,Nanchang University,Nanchang 330000,China
    2 Jiangxi Jiangtou Digital Economy Research Institute,Nanchang 330000,China
  • Published:2023-11-09
  • About author:YU Yunjun,born in 1978,Ph.D,asso-ciate professor.His main research in-terests include fault diagnosis,active disturbance rejection control(ADRC),data-driven optimal control and its applications in microgrids,and low-carbon electricity technology.
  • Supported by:
    National International Science and Technology Cooperation Project(2014DFG72240) and Key R&D Program in Jiangxi Province(20214BBG74006).

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摘要： 随着边缘设备数据的增多和神经网络的不断落地应用,边缘计算为以云计算为核心的大数据技术分担了压力。现场可编程门阵列(FPGA)因灵活的体系结构和低功耗,在边缘计算以及构建神经网络加速器中显示出优异的特性。但是,传统的基于传统卷积算法的 FPGA 解决方案往往受到片上计算单元数量的限制。使用 Zynq 作为硬件加速平台,对参数进行定点量化,利用数组分区提高流水线运行速度。采用 Winograd 快速卷积算法对传统的卷积进行改进,将卷积运算中的乘法运算转换为加法运算,降低了模型的计算复杂度,极大提高了所设计的加速器的计算性能。实验表明,XC7Z035工作在150MHz时钟下获得了 43.5GOP/s 的性能,能效是 Xeon(R) Silver 4214R 的 129倍,是双核 ARM 的 159 倍。所提方案在资源和功耗受限的情况下可以提供较高的性能,适用于网络边缘端对轻量级神经网络的落地应用。

关键词: 边缘计算, 硬件加速, 轻量级卷积神经网络, Winograd, FPGA

Abstract: With the increase of edge device data and the continuous application of neural networks,the rise of edge computing has shared the pressure on big data technologies with cloud computing as the core.Field programmable gate arrays(FPGAs) have shown excellent properties in edge computing and building neural network accelerators due to their flexible architecture and low power consumption.But traditional FPGA solutions based on traditional convolution algorithms are often limited by the number of on-chip computing units.In this paper,Zynq is used as a hardware acceleration platform,to quantize parameters at a fixed point,and array partitioning is used to improve pipeline running speed.The Winograd fast convolution algorithm is used to improve the traditional convolution,and the multiplication operation in the convolution operation is converted into an addition operation,which reduces the computational complexity of the model.The computational performance of the designed accelerator is greatly improved.Experiments show that XC7Z035 can achieve 43.5GOP/s performance under 150 MHz clock,and the energy efficiency is 129 times of Xeon(R) Silver 4214R and 159 timesof dual-core ARM.The proposedsolution is limited in resources and power consumption.It can provide high performance and is suitable for the landing application of lightweight neural networks at the edge of the network.

Key words: Edge computing, Hardware acceleration, Lightweight convolutional neural networks, Winograd, FPGA

中图分类号: 

  • TP391
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