计算机科学

计算机科学 ›› 2023, Vol. 50 ›› Issue (11): 8-14.doi: 10.11896/jsjkx.221100104

• 高性能计算 • 上一篇    下一篇

CNN景象匹配算法的加速设计与FPGA实现

王晓峰, 李超然, 路坤锋, 栾天娇, 姚娜, 周辉, 谢宇嘉   

  1. 北京航天自动控制研究所 北京 100854
    宇航智能控制技术国家级重点实验室 北京 100854
  • 收稿日期:2022-11-12 修回日期:2023-05-11 出版日期:2023-11-15 发布日期:2023-11-06
  • 通讯作者: 王晓峰(wangxf.casc@foxmail.com)
  • 基金资助:
    国家重点实验室基金(61425010302)

Acceleration Design and FPGA Implementation of CNN Scene Matching Algorithm

WANG Xiaofeng, LI Chaoran, LU Kunfeng, LUAN Tianjiao, YAO Na, ZHOU Hui, XIE Yujia   

  1. Beijing Aerospace Automatic Control Institute,Beijing 100854,ChinaNational Aerospace Intelligence Control Technology Laboratory,Beijing 100854,China
  • Received:2022-11-12 Revised:2023-05-11 Online:2023-11-15 Published:2023-11-06
  • About author:WANG Xiaofeng,born in 1995,master,engineer.His main research interest is intelligent computing.
  • Supported by:
    State Key Laboratory Fund(61425010302).

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摘要： 基于卷积神经网络的景象匹配算法较传统方法具有更高的匹配精度、更好的适应性以及更强的抗干扰能力。但是,该算法有海量的计算与存储需求,导致在边缘端部署存在巨大困难。为了提升计算实时性,文中设计并实现了一种高效的边缘端加速计算方案。在分析算法的计算特性与整体架构的基础上,基于Winograd快速卷积方法,设计了一种面向特征匹配层的专用加速器,并提出了利用专用加速器与深度学习处理器流水线式计算特征匹配层和特征提取网络的整体加速方案。在Xilinx的ZCU102开发板上进行实验发现,专用加速器的峰值算力达到576 GOPS,实际算力达422.08 GOPS,DSP的使用效率达4.5 Ope-ration/clock。加速计算系统的峰值算力达1600 GOPS,将CNN景象匹配算法的吞吐时延降低至157.89 ms。实验结果表明,该加速计算方案能高效利用FPGA的计算资源,实现CNN景象匹配算法的实时计算。

关键词: 加速计算, 景象匹配算法, 深度学习, FPGA, Winograd算法, 专用加速器

Abstract: Compared with traditional methods,the CNN-based scene matching algorithm has higher matching accuracy,better adaptability and stronger anti-interference ability.However,the algorithm has massive computing and storage requirements,which makes it difficult to deploy at the edge.To improve the real-time computing,an efficient edge-side acceleration scheme is designed and implemented.On the basis of analyzing the computation characteristics and overall architecture of the algorithm,correlation specific accelerator(CSA) is designed based on Winograd fast convolution method,and the acceleration scheme using CSA and deep-learning processor unit(DPU) pipelined computing feature correlation layer and feature extraction network is proposed.Experiments on Xilinx's ZCU102 development board finds that the peak perfor-mance of CSA reaches 576 GOPS,the actual performance reaches 422.08 GOPS,and the DSP usage efficiency reaches 4.5 Operation/clock.The peak performance of the accele-ration system reaches 1 600 GOPS,and the throughput delay of the algorithm is reduced to 157.89 ms.Experimental results show that the acceleration scheme can efficiently utilize the computing resources of the FPGA,to realize the real-time computing of the CNN-based scene matching algorithm.

Key words: Acceleration computing, Scene matching algorithm, Deep learning, FPGA, Winograd algorithm, Specific accelerator

中图分类号: 

  • TP391
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