计算机科学 ›› 2013, Vol. 40 ›› Issue (12): 31-36.
葛红美,徐超,陈念,廖希密
GE Hong-mei,XU Chao,CHEN Nian and LIAO Xi-mi
摘要: 为了解决嵌入式系统设备总线的功耗问题,从软件方面的功耗优化入手,提出一种面向嵌入式系统总线的低功耗优化方法,即在编译阶段,分别对指令地址总线和数据总线进行优化,以减少总线的翻转次数,降低其功耗。具体方法为:针对指令地址总线,采用改进后的遗传算法进行函数段调用优化,然后结合T0编码,减少总线翻转次数,从而降低其功耗。针对指令数据总线,采用粒子群算法进行指令调度优化,然后结合0-1翻转编码,减少总线翻转次数,从而降低其功耗。为了验证上述方法的正确性和有效性,以HR6P系列微处理器为平台展开实验,实验结果表明,总线功耗的优化效率达到25%左右。该方法明显减少了总线的翻转次数,提高了系统的整体性能。
[1] Jain V,Rele S,Pande S,et al.Code restructuring for improving execution efficiency,code size and power consumption for embedded DSPs[C]∥12th International Workshop on Languages and Compilers for Parallel Computing.1999 [2] Stubbs,Clyde (HI-TECH Software LLC).Compilation strate-gies for low-power designs[J].ECN Electronic Component News,2008,52(9):29-30 [3] Stubbs,Clyde (HI-TECH Software).Compilation strategies:Alternate approaches to achieve low power consumption[J].ECN Electronic Component News,n SUPPL.,2008(4):11-13 [4] Jiang Xiang-tao,Hu Zhi-gang,He Jian-biao.Call chain analysis for low power compile optimization[J].Journal of Jilin University (Engineering and Technology Edition),2009,39(1):143-147 [5] Lorenz M,Leupers R,Marwedel P,et al.Low-energy DSP code generation using a genetic algorithm[C]∥Proceedings-IEEE International Conference on Computer Design:VLSI in Computers and Processors.2001:431-437 [6] Parikh A,Kim S,Kandemir M,et al.Instruction Scheduling forLow Power[J].The Journal of VLSI Signal Processing,2004,37(1):129-149 [7] Lee C,Lee J K,Hwang T T.Compiler optimization on Instruction Scheduling for Low Power[C]∥ISSS2000.2000:20-22 [8] Shao Z,Zhuge Q,Zhang Y,et al.Efficient Scheduling for Low-Power High-Performance DSP Applications[J].International Journal of High Performance Computing and Networking IJHCN,2004,1:3-16 [9] Lakshminarayana G,Raghunathan A,Jha N K.IncorporatingSpeculative Execution into Scheduling of Control-Flow-Intensive Designs[J].IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems,2000,19(3):308-324 [10] Chung E-Y,Benini L,De Micheli G.Energy Efficient SourceCode Transformation based on Value Profiling[C]∥Iit wnrhhnp fw Cnmpilen and Opemtmng Syrtcm fw Lnrn-Pmncr.2000:1-7 [11] Stan M R,Burleson W P.Bus-invert coding for low power I/O[J].Microelectronics Reliability,1996,36(4) [12] Lv T,Henkel J,Lekatsas H,et al.An adaptive dictionary encoding scheme for SOC data buses[M].Design,Automation and Test in Europe Conference and Exhibition,2002:1059-1064 [13] Benini L,De Micheli G.System-Level Power Optimization Techniques and Tools[J].ACM TODAES,2000,5(2):115-182 [14] Mehta H,Owens R M,Irwin M J.Some Issues in Gray CodeAddressing[C]∥Proceedings of the 6th Great Lakes Symposium on VLSI.1996:178 [15] Gu Ji,Guo Hui.An 3fficient segmental bus-invert coding method for instruction memory data bus switching reduction[C]∥EURASIP Journal on embedded Systems.2009:20-29 [16] Suresh D C,Agrawal B,Yang J,et al.Power Efficient Encoding Techniques for Off-Chip Data Buses[C]∥Proc.of Compilers and Architecture and Synthesis for Embedded Systems (CASES).San Jose,CA,Oct.2003 [17] Julien N,et al.Power consumption modeling and characterization of the TI C6201[C]∥IEEE Micro.2003:40-49 [18] Lorenz M,et al.Compiler based Exploration of DSP Energy Savings by SIMD Operations[C]∥Asia South Pacific Design Automation Conference C.Yokohama,Japan,2004:838-841 |
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