计算机科学 ›› 2013, Vol. 40 ›› Issue (4): 31-34.

• 2012多值逻辑专栏 • 上一篇    下一篇

前导1预测算法的设计与实现

李星,胡春媚,李勇,李振涛   

  1. 国防科技大学计算机学院长沙410073;国防科技大学计算机学院长沙410073;国防科技大学计算机学院长沙410073;国防科技大学计算机学院长沙410073
  • 出版日期:2018-11-16 发布日期:2018-11-16
  • 基金资助:
    本文受国家自然科学基金(60906014)资助

Design and Implementation of Leading-One Prediction

LI Xing,HU Chun-mei,LI Yong and LI Zhen-tao   

  • Online:2018-11-16 Published:2018-11-16

摘要: 前导1预测(Leading One Prediction,LOP)算法常被用在浮点数的加减运算中,它能与尾数加法器并行工作,从而加快了尾数加法器计算结果的规格化过程,同时,这种方法会带来最多1位的误差。根据对误差的处理方式不同,将预测算法分成了3类,并详细介绍了其中的串行纠错前导1预测算法的具体结构,对其关键的组成部分在算法上进行了选择和优化。它与并行纠错LOP以及传统前导1检测(Leading One Detector,LOD)的逻辑综合的实验结果表明,该算法取得了面积、功耗和延时之间的较好均衡。在实际的应用中,该算法成功地运用在了工作频率为1GHz的三站式双通路(Two-Path)浮点加法器中。

关键词: 前导1预测,前导1检测,纠错,规格化

Abstract: Leading-one prediction(LOP),which is often used in floating-point addition/subtraction,can operate in parallel with the adder and reduce the delay in the normalization shift.However,this prediction might generate one-bit-error.Three different LOP architectures were classified by the methods handling the one-bit-error.Among that,the LOP architecture with serial correction was described in detail.At the same time,serial correction’s key components in the algorithms were optimized.Through the synthesis experiments of LOP architecture with concurrent correction,serial correction and traditional leading one detector(LOD) method,we found that serial correction method has the best performance balancing area,power and delay.It is successfully used in two-path floating-point adder which is operated in 3-cycle pipeline with a 1Ghz clock frequency.

Key words: Leading one prediction,Leading one detection,Correction,Normalization

[1] Bruguera J D,Lang T.Leading-One Prediction with Concurrent Position Correction[J].IEEE Transactions on Computers,1999,48(10):298-305
[2] Ji Rong,Ling Zhi-qiang,Zeng Xian-jun,et al.Comments onLeading-One Prediction with Concurrent Position Correction[J].IEEE Transaction on Computer,2009,58(12)
[3] Suzuki H,Morinaka H,Makino H,et al.Leading Zero Anticipatory Logic for High Speed Floating-Point Addition[J].IEEE Journal of Solid State Circuits,1996,31(8):1157-1164
[4] Schmookler M S,Nowka K J.Leading zero anticipation and detection:A comparision of methods.Colorado[C]∥Proc.of the 15th IEEE Symposium on Computer Arithmetic.July 2001:7-12
[5] Dimitrakopoulos G,Galanopoulos K,Mavrokefalidis C,et al.Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units[J].IEEE Transactions on Very Large Scale Integration System,2008,16(7)
[6] Lee K T,Nowkda K J.1GHz leading-zero anticipator using independent sign-bit determination logic[C]∥Symposium on VLSI Circuit Digest of Technical Papers.2000
[7] Zhang Ge,Hu Wei-wu,Qi ZI-chu.Parallel Error Detection for Leading Zero Anticipation[J].J.Comput.Sci.&Technol,2006,1(6):901-906
[8] Yao Tao,Gao De-yuan.A Novel Concurrent Error DetectionCircuit for Leading Zero Anticipator[C]∥2nd Intermational Conference on Computer Engineering and Technology.2010
[9] Oklobdzija V.An Algorithmic and Novel Design of a LeadingZero Detector Circuit:Comparison with Logic Synthesis[J].IEEE Transactions on VLSI System,1993,2(1):124-128
[10] Hinds C N,Lutz D R.A Small and Fast Leading One Predictor Corrector Circuit[C]∥Asilomar Conference on Signals,Systems and Computers.2005:1181-1185
[11] Oberman S F,Flynn M J.A variable Latency Pipelined Floating-point Adder[R].CSL-TR-96-689.Stanford University,1996
[12] 黄迟.64位高速浮点加法器的VLSI实现和结构研究[D].上海:复旦大学,2004
[13] 王颖.高性能CPU中浮点加法器的设计与实现[D].上海:同济大学,2005

No related articles found!
Viewed
Full text


Abstract

Cited

  Shared   
  Discussed   
No Suggested Reading articles found!