基于PTM模型与BN模型的电路可靠性计算方法比较

计算机科学 ›› 2015, Vol. 42 ›› Issue (Z6): 115-117.

基于PTM模型与BN模型的电路可靠性计算方法比较

蒋玉芳,邓左祥

广西现代职业技术学院建筑与信息工程系河池547000,上海交通大学电子信息与电气工程学院上海200240

出版日期:2018-11-14 发布日期:2018-11-14

Comparison of Circuit Reliability Calculation Methods Based on PTM Model and BN Model

JIANG Yu-fang and DENG Zuo-xiang

Online:2018-11-14 Published:2018-11-14

摘要/Abstract

摘要： 现代工艺的发展使得集成电路在获得高性能的同时,也更容易受到软差错的影响。针对软差错影响下电路的可靠性问题,选取了二种典型的基于条件概率理论的门级评估方法:BN方法和PTM方法,分别介绍了其原理,并结合实验分析了它们各自的功能、适用范围以及复杂度,且指出了下一步的研究思路。

Abstract: The development of VLSI technology results in the dramatical improvement of the performance of integrated circuits,and integrated circuits become more susceptible to soft errors.For the reliability of circuits under the soft error,two typical gate-level estimation methods based on the conditinal probability,named PTM method and BN mehod separately,were chosen in this paper.The principles of the two methods were introduced,and the function,applicability and complexity were analyzed respectively by combining the experiemnts.Finally,the results were concluded,and the future research was illuminated.

Key words: BN method,PTM method,Elementary gate,Circuit reliability

蒋玉芳,邓左祥. 基于PTM模型与BN模型的电路可靠性计算方法比较[J]. 计算机科学, 2015, 42(Z6): 115-117. https://doi.org/

JIANG Yu-fang and DENG Zuo-xiang. Comparison of Circuit Reliability Calculation Methods Based on PTM Model and BN Model[J]. Computer Science, 2015, 42(Z6): 115-117. https://doi.org/

参考文献

[1] Hennessy John L,Patterson David A.Computer architecture:a quantitative approach [M].Elsevier,2012
[2] 肖杰.结合版图结构信息的门级电路可靠性评估方法的研究 [D].上海:同济大学,2013
[3] Karthikeyan L,Sanjukta B.An error model to study the behavior of transient errors in sequential circuits[C]∥Proceedings of the 22nd International Conference on VLSI Design,New Delhi.IEEE Computer Society:Los Alamitos,2009,485-490
[4] Thara R,Karthikeyan L,Sanjukta B.Probabilistic error modeling for nano-domain logic circuits [J].IEEE Transactions on Very Large Scale Integration Systems,2009,17(1):55-65
[5] Smita K,Viamontes George F,Markov Igor L,et al.Accuratereliability evaluation and enhancement via probabilistic transfer matrices[C]∥Proceedings of the the Conference on Design Automation and Test in Europe,Munich.IEEE Computer Society:Los Alamitos,2005,282-287
[6] Xiao Jie,Jiang Jian-hui,Zhu Xu-guang,et al.A method of gate-level circuit reliability estimation based on iterative PTM model[C]∥Proceedings of the IEEE 17th Pacific Rim International Symposium on Dependable Computing,Pasadena,USA .IEEE Computer Society:Los Alamitos,2011,276-277
[7] 肖杰,江建慧.考虑时间因素的不同基本门故障概率计算 [J].电子学报,2013,41(4):666-673
[8] Yu Chien-Chih.Probabilistic Analysis for Modeling and Simulating Digital Circuits [D].Michigan:The University of Michigan,2012
[9] L Levin V.Probability analysis of combination systems and their reliability [J].Engineering Cyberneitcs,1996,11(6):78-84
[10] Michael B,Agrawal Vishwani D.Essentials of electronic testing for digital,memory,and mixed-signal VLSI circuits [M].Springer,2000

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