计算机科学 ›› 2018, Vol. 45 ›› Issue (2): 249-253.doi: 10.11896/j.issn.1002-137X.2018.02.043

• 软件与数据库技术 • 上一篇    下一篇

一种基于海明排序进行无关位填充的低功耗测试向量优化方法

谈恩民,范玉祥   

  1. 桂林电子科技大学电子工程与自动化学院 广西 桂林541004,桂林电子科技大学电子工程与自动化学院 广西 桂林541004
  • 出版日期:2018-02-15 发布日期:2018-11-13

Optimization Method of Low Power Test Vectors Based on Hamming Sorting for X Bits Padding

TAN En-min and FAN Yu-xiang   

  • Online:2018-02-15 Published:2018-11-13

摘要: 集成电路在测试过程中的测试功耗通常会远远高于集成电路正常工作时的功耗,而过高的测试功耗可能会造成电路损坏或是芯片烧毁。为了降低测试功耗,提出了一种基于海明排序进行无关位填充的低功耗测试向量优化方法。首先,对测试集中的测试向量按照无关位含量由多到少进行排序;然后,将测试向量按照海明距离由小到大进行排序;最后,对排序后的测试集进行无关位的合理填充,使得测试向量之间的相关性增大,从而降低测试功耗。以ISCAS’85国际标准电路作为测试对象进行,结果表明,相比于使用优化前的测试集,运用优化后的测试集明显降低了测试功耗。

关键词: 测试向量,海明距离,无关位,低功耗设计

Abstract: The test power consumption in the process of integrated circuit testing is usually much higher than the normal power consumption of the integrated circuit.However,the high test power consumption may cause the circuit to be damaged or the chip to be burned.An optimization method of low power test vectors based on Hamming sorting for X bits padding was proposed to reduce the test power consumption.Firstly,the test vectors in the test set are ranged from high X bits to low X bits.Then,the test vectors are sorted in ascending order according to the Hamming distance.Finally,the test power consumption is reduced by padding X bits for the sorted test set reasonably,which increases the correlation between test vectors.The ISCAS’85 standard circuit was used as the test object.The experimental results show that compared with using the non-optimized test set,the test power consumption is reduced obviously with the optimized test set.

Key words: Test vector,Hamming distance,X bits,Low power design

[1] CHEN T,YI X,ZHENG L Y,et al.Low Power Deterministic Test Scheme Based on Viterbi[J].Journal of Computer-Aided Design and Computer Graphics,2016,28(5):821-829.(in Chinese) 陈田,易鑫,郑浏旸,等.基于Viterbi的低功耗确定性测试方案[J].计算机辅助设计与图形学学报,2016,28(5):821-829.
[2] ZHU M,YANG C L,KONG D J.Extraction and Optimization of Analog Circuit Built-in Self Test Fault Features[J].Chinese Journal of Scientific Instrument,2013,34(1):200-207.(in Chinese) 朱敏,杨春玲,孔德晶.模拟电路内建自测试故障特征提取与优化[J].仪器仪表学报,2013,34(1):200-207.
[3] WU G L,HU C,LI R.An Efficient BIST Scheme for ADC Testing[J].Chinese Journal of Electron Devices,2003,26(2):190-193.(in Chinese) 吴光林,胡晨,李锐.一种有效的ADC内建自测试方案[J].电子器件,2003,26(2):190-193.
[4] YUAN H,GUO K,SUN X,et al.A Power Efficient BIST TPG Method on Don’t Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering[J].Journal of Electronic Testing,2015,31(1):43-52.
[5] LI P,YAN X L.Low Power Deterministic Vectors Generation Research Based on Configurable LFSR[J].Microelectronics & Computer,2013,30(10):144-148,152.(in Chinese) 李鹏,颜学龙.基于可配置LFSR的低功耗确定性矢量生成技术的研究[J].微电子学与计算机,2013,30(10):144-148,152.
[6] SHANG J,ZHANG L.Test Data Compression Scheme Based on Compatible Data Block Coding[J].Information Technology Journal,2013,12(1):204-208.
[7] GIRARD P,GUILLER L,LANDRAULT C,et al.A modified clock scheme for a low power BIST test pattern generator[C]∥Proceedings of the 19th on VLSI Test Symposium.2001:306-311.
[8] LUO Z Y,MIN Y H,YANG S Y.A Novel ATPG Approach to Maxmum Power Estimation of CMOS Circuits[J] Journal of Computer Research and Development,2001,8(12):1418-1422.(in Chinese) 骆祖莹,闵应骅,杨士元.一种新的CMOS电路最大功耗估计方法[J].计算机研究与发展,2001,8(12):1418-1422.
[9] SONG H B,SHI Y H.Testing Techniques of Low Power BIST for VLSI[J].Chinese Journal of Electron Devices,2002,25(1):101-104.(in Chinese) 宋慧滨,史又华.面向低功耗BIST的VLSI可测性设计技术[J].电子器件,2002,25(1):101-104.
[10] YAN X L,XIONG J C.A Varible-run-length Coding Compression Method of X-filling[J].Microelectronics & Computer,2015,32(10):134-136,142.(in Chinese) 颜学龙,熊杰超.一种变游程编码的X位填充压缩方法[J].微电子学与计算机,2015,32(10):134-136,142.
[11] KAJIHARA S,MIYASE K.On identifying don’t care inputs of test patterns for combinational circuits[C]∥IEEE/ACM International Conference on Computer Aided Design.2001:364-369.
[12] CHANDRA A,CHAKRABARTY K.Low-power scan testing and test data compression for system-on-a-chip[J].IEEE Tran-sactions on Computer-Aided Design of Integrated Circuits and Systems,2002,1(5):597-604.
[13] XU S Z,LIANG H G,GU W Y,et al.A Test Compression Method of Power Law Division Based on Dynamic Assignment of Don’t Care Bits[J].Journal of Computer Research and Deve-lopment,2010,7(Suppl.):181-184.(in Chinese) 徐三子,梁华国,顾婉玉,等.基于无关位动态赋值的幂次划分测试压缩方案[J].计算机研究与发展,2010,7(Suppl.):181-184.
[14] WANG J J ,WANG G L.Design and Implementation of Low-power Consumption Node in LR-WPAN[J].Journal of Chongqing University of Technology (Natural Science),2012,6(12):74-78.(in Chinese) 王俊杰,王冠凌.LR-WPAN低功耗节点设计与实现[J].重庆理工大学学报(自然科学),2012,6(12):74-78.

No related articles found!
Viewed
Full text


Abstract

Cited

  Shared   
  Discussed   
No Suggested Reading articles found!