计算机科学 ›› 2018, Vol. 45 ›› Issue (3): 305-310.doi: 10.11896/j.issn.1002-137X.2018.03.050

• 交叉与前沿 • 上一篇    下一篇

片上网络容错技术研究

李璐璐,裘雪红,周端,张剑贤   

  1. 西安电子科技大学计算机学院 西安710071,西安电子科技大学计算机学院 西安710071,西安电子科技大学计算机学院 西安710071,西安电子科技大学计算机学院 西安710071
  • 出版日期:2018-03-15 发布日期:2018-11-13
  • 基金资助:
    本文受国家自然科学基金项目(61474087)资助

Research on Fault Tolerant Technology for Networks-on-Chip

LI Lu-lu, QIU Xue-hong, ZHOU Duan and ZHANG Jian-xian   

  • Online:2018-03-15 Published:2018-11-13

摘要: 片上网络是一种全新的片上计算机体系结构,对片上网络的研究主要包括拓扑结构、路由算法、服务质量、交换机制、拥塞控制、能耗和容错等突出问题,其中对容错方法的研究一直是研究的重点。在软件改进和硬件改进方面,容错方法可以分为路由算法容错和路由器结构容错两类。分析当前已有容错方法的适用情况、实现原理和实现方法,并且分析其延迟、吞吐率、功耗等性能及其优缺点,对容错方法的现状进行剖析并且为容错方法的下一步研究提供研究方向。

关键词: 片上网络,容错,路由算法,性能分析

Abstract: Network-on-chip is a new computer architecture on chip,the study of network-on-chip mainly includes topo-logical structure,routing algorithm,service quality,switching mechanism,congestion avoidance,energy consumption,fault tolerant and so on,and the study of fault tolerant methods is the most important research issue.This paper divided fault tolerant methods into two types:tolerant fault by algorithms and tolerant fault by architecture, from the aspects of software improvement and hardware improvement.This paper analyzed the application conditions,implementation principles and implementation methods of the existing falut tolerant routing algorithms,analyzed the performance of communication latency,throughput and power consumption,and advantages and disadvantages of the existing falut tolerant methods,dissected the situation of the existing falut tolerant methods and offered a possible research orientation.

Key words: Network-on-Chip,Falut tolerant,Routing algorithm,Performance analysis

[1] KIA H S,ABABEI C,SRINIVASAN S,et al.A new scalablefault tolerant routing algorithm for networks-on-chip[C]∥IEEE,International Midwest Symposium on Circuits and Systems.IEEE,2015.
[2] GE F,WU N,WAN Y.A Network Monitor based DynamicRouting Scheme for Network on Chip[C]∥Proc.Asia Pacific Conf.on Postgraduate Research in Microelectronics and Electronics.2009:133-136.
[3] ZHANG Z,GREINER A,TAKTAK S.A reconfigurable routing algorithm fora fault-tolerant 2D-mesh Network-on-Chip[C]∥Design Automation Conference.2008:441-446.
[4] VALINATAJ M,MOHAMMADI S,SAFARI S.Fault-awareand Recon-figurable Routing Algorithms for Networks-on-Chip[J].IETE Journal of Research,2011,57(3):215-224.
[5] ZHU H,PANDE P P,GRECU C.Performance evaluation of adaptive routing algorithms for achieving fault tolerance in NoC fabrics[C]∥Application Specific Systems,Architectures and Processors.2007:42-47.
[6] GONG J H,WANG W J.Research on fault tolerant routingmethod for faulty links in networks-on-chip[J].Application Research of Computers,2016,33(5):1415-1418.(in Chinese) 龚健虎,王闻今.片上网络中面向链路故障的容错路由方法研究[J].计算机应用研究,2016,33(5):1415-1418.
[7] VALINATAJ M,MOHAMMADI S,PLOSILA J,et al.Areconfigurable and adaptive routing method for fault-tolerant mesh-based networks-onchip[J].International Journal of Electronics and Communications,2011,65(7):630-640.
[8] WANG Y F.Study of Fault Tolerant Routing Algorithms for Three Dimensional Networks-on-chip[D].Qufu:Qufu Normal University,2015.(in Chinese) 王宇飞.3D NoC容错路由算法的研究[D].曲阜:曲阜师范大学,2015.
[9] EBRAHIMI M,DANESHTALAB M,PLOSILA J.Fault-tole-rant routing algorithm for 3D NoC using Hamiltonian path stra-tegy[C]∥ Design,Automation & Test in Europe Conference & Exhibition.IEEE,2013:1601-1604.
[10] LEE D,PARIKH R,BERTACCO V.Highly Fault-tolerant NoC Routing with Application-aware Congestion Management[C]∥International Symposium on Networks-On-Chip.ACM,2015:1-8.
[11] SANCHO J,ROBLES A,DUATO J.An effective methodology to improve the performance of the Up*/Down* routing algorithm[J].IEEE Transactions on Parallel and Distributed Systems,2014,5(8):740-754.
[12] KINSY M A,CHO M H,SHIM K S,et al.Optimal and heuristic application-aware oblivious routing[J] .IEEE Transactions on Computers,2012,2(1):59-73.
[13] PALESI M,LONGO G,SIGNORINO S,et al.Design of bandwidth aware and congestion avoiding efficient routing algorithms for networks-on-chip platforms[C]∥ ACM/IEEE International Symposium on Networks-On-Chip.IEEE Computer Society,2008:97-106.
[14] BEN AHMED A,BEN A A.Deadlock-Recovery Support forFault-tolerant Routing Algorithms in 3D-NoC Architectures[C]∥IEEE,International Symposium on Embedded Multicore Socs.2013:67-72.
[15] SIBAI F N.On-Chip Network for Interconnecting Thousands of Cores[J].IEEE Transactions on Parallel and Distributes Systems,2012,23(2):193-201.
[16] QU L X,LIU H P,PAN N Z,et al.Fault-tolerant Routing Algorithm of NoC[J].Electronics & Packaging,2015(9):21-23.(in Chinese) 屈凌翔,刘海鹏,潘能智,等.基于NoC的容错路由算法[J].电子与封装,2015(9):21-23.
[17] AKBARI S,SHAFIEE A,FATHY M,et al.AFRA:A low cost high performance reliable routing for 3D mesh NoCs[C]∥Design,Automation & Test in Europe Conference & Exhibition.IEEE,2012:332-337.
[18] OUYANG Y M,OUYANG X Y,LIANG H G,et al.3D NoC Deflection Fault-tolerant Routing Method Based on Dynamic Priority [J].Journal of Computer-Aided Design & Computer Graphics,2014,26(3):486-492.(in Chinese) 欧阳一鸣,欧阳小叶,梁华国,等.基于动态优先级的3D NoC偏转路由容错方法[J].计算机辅助设计与图形学学报,2014,26(3):486-492.
[19] FENG C C,LU Z H,JANTSCH A,et al.FoN:fault-on-neighbor aware routing algorithm for networks-on-chip [C]∥Proceedings of IEEE International SoC Conference.Los Alamitos:IEEE Computer Society Press,2010:441-446.
[20] FENG C C,ZHANG M X,LI J W,et al.A low-overhead fault-aware deflection routing algorithm for 3D network-on-chip[C]∥Proceedings of International Symposium on Quality Electronic Design.Piscataway N J:IEEE Press,2011:19-24.
[21] DANG K N,MEYER M,OKUYAMA Y,et al.A low-overhead soft-hard fault-tolerant architecture,design and management scheme for reliable high-performance many-core 3D-NoC systems[J].Journal of Supercomputing,2017,73(6):2705-2729.
[22] AHMED A B,ABDALLAH A B.LA-XYZ:Low Latency,High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture[C]∥IEEE,International Symposium on Embedded Multicore Socs.IEEE,2012:167-174.
[23] DANG K N,MEYER M,OKUYAMA Y,et al.Soft-error resi-lient 3D Network-on-Chip router[C]∥IEEE,International Conference on Awareness Science and Technology.IEEE,2015:84-90.
[24] BEN A A,BEN A A.Adaptive fault-tolerant architecture androuting algorithm for reliable many-core 3D-NoC systems[J].Journal of Parallel & Distributed Computing,2016,93(1):30-43.
[25] SILVEIRA J,BODIN M,FERREIRA J M,et al.A fault prediction module for a fault tolerant NoC operation[C]∥ International Symposium on Quality Electronic Design.IEEE,2015:284-288.
[26] DAI L,SHANG D,XIA F,et al.Monitoring circuit based onthreshold for fault-tolerant NoC[J].Electronics Letters,2010,46(14):984-985.
[27] YUAN W L.A Fault-Tolerant Design for TSV and Crossbar in 3D NoC [D].Hefei:Hefei University of Technology,2013.(in Chinese) 袁吴铃.3D NoC中TSV和交叉开关的容错设计[D].合肥:合肥工业大学,2013.
[28] OUYANG Y M,WANG Q,LIANG H G,et al.Link adaptive fault-tolerant method based on fault granularity partition in NoC [J].Journal of Electronic Measurement and Instrumentation,2015(8):1102-1113.(in Chinese) 欧阳一鸣,王悄,梁华国,等.基于故障粒度划分的NoC链路自适应容错方法[J].电子测量与仪器学报,2015(8):1102-1113.
[29] OUYANG Y M,ZHANG Y D,LIANG H G,et al.Fault-Tole-rant Router for 3D NoC Based on virtual channel Fault Granularity Partition[J].Journal of Computer Research and Development,2014,3(9): 1073-1076.(in Chinese) 欧阳一鸣,张一栋,梁华国,等.基于虚通道故障粒度划分的3D NoC容错路由器设计[J].计算机研究与发展,2014,3(9):1073-1076.
[30] OUYANG Y M,HE M,LIANG H G,et al.A Fault-Tolerant Architecture Design of Fault-Aware RVOQ in Three-Dimensional Network-on-Chip[J].Journal of Computer-Aided Design &Computer Graphic,2015,27(1):192-200.(in Chinese) 欧阳一鸣,何敏,梁华国,等.3D NoC中故障感知的RVOQ容错架构设计[J].计算机辅助设计与图形学学报,2015,27(1):192-200.
[31] ZHANG S J,HAN G D,SHEN J L,et al.Fault-tolerant Routing Algorithm of NoC Based on Buffer Reuse of Faulty Links [J].Journal of Computer-Aided Design & Computer Graphics,2014,26(1):131-137.(in Chinese) 张士鉴,韩国栋,沈剑良,等.基于故障链路缓存再利用的NoC容错路由算法[J].计算机辅助设计与图形学学报,2014,26(1):131-137.

No related articles found!
Viewed
Full text


Abstract

Cited

  Shared   
  Discussed   
No Suggested Reading articles found!