计算机科学

计算机科学 ›› 2024, Vol. 51 ›› Issue (11A): 231100120-7.doi: 10.11896/jsjkx.231100120

• 计算机软件&体系架构 • 上一篇    下一篇

基于FPGA并行实现SVM训练的可重构计算系统

彭卫东1, 郭威1, 魏麟2   

  1. 1 中国民用航空飞行学院航空电子电气学院 四川 广汉 618300
    2 中国民用航空飞行学院飞行技术学院 四川 广汉 618300
  • 出版日期:2024-11-16 发布日期:2024-11-13
  • 通讯作者: 郭威(fpga2516@163.com)
  • 作者简介:(893745910@qq.com)
  • 基金资助:
    民航飞行技术与飞行安全重点实验室自主研究项目(XYKY2023018);民机综合航电技术研究所科研创新团队项目(CZKY2023161)

Reconfigurable Computing System for Parallel Implementation of SVM Training Based on FPGA

PENG Weidong1, GUO Wei1, WEI Lin2   

  1. 1 Institute of Electronic and Electrical Engineering,Civil Aviation Flight University of China,Guanghan,Sichuan 618300,China
    2 Institute of Flight Technology,Civil Aviation Flight University of China,Guanghan,Sichuan 618300,China
  • Online:2024-11-16 Published:2024-11-13
  • About author:PENG Weidong,born in 1968,professor.His main research interests include computer measurement and control and computer simulation.
    GUO Wei,born in 1998,postgraduate.His main research interests include embedded system and machine learning acceleration.
  • Supported by:
    Independent Research Project of Key Laboratory of Flight Techniques and Flight Safety(XYKY2023018) and Research and Innovation Team Project of Civil Aircraft Integrated Avionics Technology Research Institute(CZKY2023161).

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摘要： 针对支持向量机在处理大规模数据集时所面临的计算复杂度高和训练时间长的问题,设计了一种基于FPGA并行实现支持向量机训练的可重构计算系统,并分析了不同量化方式下的硬件资源消耗与加速性能。通过采用随机梯度下降法训练支持向量机,使得需要求解的维度与样本的维度相关联,相较于传统的基于二次规划的求解方法可以显著降低计算复杂性。同时,利用基于FPGA的可重构硬件平台设计了专用并行计算结构以加速支持向量机的训练过程。对设计的完整系统进行了软硬件联合仿真,在4个公共数据集上的仿真结果表明,整体模型预测准确率达到90%以上;在训练阶段,相较于采用相同算法的软件实现,所提出的浮点数表示下硬件实现的单个样本处理时间至少减少了2个数量级;定点数表示下硬件实现的单个样本处理时间最大减小了3个数量级;与基于二次规划问题求解的硬件实现相比,单个样本处理速度最快提升了394倍。

关键词: 现场可编程逻辑门阵列, 支持向量机, 可重构系统, 并行计算, 随机梯度下降法

Abstract: To address the problems of high computational complexity and long training time faced by support vector machines when dealing with large-scale datasets,a reconfigurable computing system for parallel SVM training based on FPGA is designed.The hardware resource consumption and acceleration performance under different quantization methods are analyzed.By utilizing the stochastic gradient descent method for SVM training,the dimensions to be solved are associated with the sample dimensions,significantly reducing computational complexity compared to traditional quadratic programming-based methods.Additionally,a specialized parallel computing structure is designed using FPGA-based reconfigurable hardware platform to accelerate the SVM training process.The entire system is jointly simulated in software and hardware.Simulation results on four public datasets show that the overall model prediction accuracy exceeds 90%.During the training phase,compared to software implementation using the same algorithm,the proposed hardware implementation reduces the processing time for a single sample by at least two orders of magnitude under floating-point representation.Under fixed-point representation,the processing time for a single sample is reduced by up to three orders of magnitude.Compared to the hardware implementation based on quadratic programming problem solving,the processing speed for a single sample is improved by up to 394 times.

Key words: FPGA, Support vector machine, Reconfigurable system, Parallel computing, Stochastic gradient descent

中图分类号: 

  • TP181
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