Computer Science ›› 2016, Vol. 43 ›› Issue (5): 9-12.doi: 10.11896/j.issn.1002-137X.2016.05.002

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Reliability Analysis of Circuit under Soft Error

WANG Zhen and JIANG Jian-hui   

  • Online:2018-12-01 Published:2018-12-01

Abstract: With the coming of the big data era,people demand more reliable microprocessor.While the intensive techno-logy scaling make the circuit encounter greater sensitivity to soft errors.It’s very important to analyze the reliability of the circuit under soft errors.This paper gave a survey on the reliability analysis methods,which are categorized into circuit-level,gate-level,register-transfer-level(RTL) and architecture-level,and introduced and compared these methods according to method property in each level.

Key words: Reliability analysis,Circuit level,Gate level,RTL,Architecture level

[1] Eaton P,Benedetto J,Mavis D,et al.Single event transient pulse width measurements using a variable temporal latch technique [J].IEEE Trans.on Nuclear Science,2004,51(6):3365-3368
[2] Messenger G C.Collection of charge on junction nodes from ion tracks [J].IEEE Trans.on Nuclear Science,1982,29(6):2024-2031
[3] Alexandrescu D,Anghel L,Nicolaidis M.New methods for eva-luating the impact of single event transients in VDSM ICs[C]∥Proc.of the 17th IEEE Int.Symp.on Defect and Fault Tolerance in VLSI Systems.Vancouver,2002:99-107
[4] Rao R R,Chopra K,Blaauw D T,et al.Computing the soft errorrate of a combinational logic circuit using parameterized descriptors [J].IEEE Trans.on Computer-Aided Design of Integrated Circuits and Systems,2007,26(3):468-479
[5] Watkins A,Tragoudas S.Transient pulse propagation using the weibull distribution function[C]∥IEEE Int’l Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems(DFT).Austin,TX,USA,2012:109-114
[6] Ramanarayanan R,Degalahal V,Vijaykrishnan N,et al.Analysis of soft error rate in flip-flops and scannable latches[C]∥IEEE Int.SOC Conference.Portland,2003:231-234
[7] Zhang M,Shanbhag N R.A soft error rate analysis(SERA)methodology[C]∥Proc.of International Conf.on Computer Aided Design.Taipei,Taiwan,2004:111-118
[8] Rajaraman R,Kim J S,Vijaykrishnan N,et al.SEAT-LA:A soft error analysis tool for combinational logic[C]∥Proceedings of the 19th International conference on VLSI Design.Hyderabad,India,2006:499-502
[9] Hubert G,Palau J M,Castellani-Coulie K,et al.Detailed analysis of secondary ions’ effect for the calculation of neutron-induced SER in SRAMs[J].IEEE Trans.on Nuclear Science,2001,48(6):1953-1959
[10] Hubert G,et al.Prediction of transient induced by neutron/proton in CMOS combinational logic cells[C]∥12th IEEE Int.On-Line Testing Symposium,Lake of Como..Italy,2006
[11] Xuan X,Chatterjee A.Sensitivity and reliability evaluation for mixed-signal ICs under electromigration and hot-carrier effects[C]∥IEEE Int’l Symp.On Defect and Fault Tolerance in VLSI Systems.San Francisco,California,2001:323-328
[12] Ramakrishnan K,Rajaraman R,Suresh S,et al.Variation impact on SER of combinational circuits[C]∥The 8th International Symposium on Quality Electronic Design(ISQED’07).San Jose,2007:911-916
[13] Zhao C,Bai X L,Dey S.Evaluating transient error effects in digi-tal nanometer circuits[J].IEEE Trans.on Reliability,2007,56(3):381-391
[14] Sonza R M,Violante M.Accurate and efficient analysis of single event transients in VLSI circuits[C]∥IEEE Int’l On-Line Testing Symposium.Kos Island,Greece,2003:101-105
[15] Zhang Bin,Wang Wei-shen,Orshansky M.FASER:fast analysis of soft error susceptibility for cell-based designs[C]∥The 7th Int’l Symp.on Quality Electronic Design(ISQED’06).San Jose,CA,USA,2006:755-760
[16] Zhang Ming,Shanbhag N R.Soft-error-rate-analysis(SERA)methodology [J].IEEE Trans.on Computer-Aided Design of Integrated Circuits and Systems,2006,25(10):2140-2155
[17] Mohanram K,Touba N A.Cost-Effective Approach for Redu-cing Soft Error Failure Rate in Logic Circuits[C]∥International Test Conference.Charlotte,NC,USA,2003:893-901
[18] Nieuwland A K,Jasarevic S,Jerin G.Combinational logic softerror analysis and protection[C]∥The 12th IEEE Int’l On-line Testing Symposium.Lake of Como,Italy,2006:99-104
[19] Sub K J,Nicopoulos C,Vijakrishnan N,et al.A probabilistic model for soft-error rate estimation in combinational logic[C]∥Proc.of the 1st Int Workshop on Probabilistic Analysis Techniques for Real Time and Embedded Systems.Italy,2004:25-31
[20] Asadi G,Tahoori M B.An analytical approach for soft error rate estimation in digital circuits[C]∥IEEE Int Symp on Circuits and Systems.Kobe,2005:2991-2994
[21] Krishnaswamy S,Viamontes G F,Markov I L,et al.Accurate reliability evaluation and enhancement via probabilistic transfer matrices[C]∥Proc of the Design,Automation and Test in Europe Conference and Exhibition.Orlando,2005:282-287
[22] Wang Zhen,Jiang Jian-hui,Yang Guang.Implementation andanalysis of probabilistic methods for gate-level circuit reliability estimation[J].Tsinghua Science and Technology,2007,12(S1):32-38
[23] Abdollahi A.Probabilistic decision diagrams for exact probabilistic analysis[C]∥Proc.Int’l Conference on Computer Aided Design.San Jose,CA,2007:266-272
[24] Wang Zhen,Jiang Jian-hui.A serial method of circuit reliability calculation based on probabilistic transfer matrix[J].Chinese Journal of Electronics,2009,37(2):241-247(in Chinese) 王真,江建慧.基于概率转移矩阵的串行电路可靠度计算方法[J].电子学报,2009,7(2):241-247
[25] Xiao J,Jiang J,Zhu X,et al.A method of gate-level circuit reliability estimation based on iterative PTM model[C]∥IEEE 17th Pacific Rim International Symposium on Dependable Computing.Pasadena,USA,2011:276-277
[26] Asadi H,Tahoori M B.Soft error modeling and protection for sequential elements[C]∥The 20th IEEE Int’l Symposium on Defect and Fault Tolerance in VLSI Systems.Monterey,USA,2005:463-474
[27] Mohyuddin N,Pakbaznia E,Pedram M.Probabilistic error propa-gation in logic circuits using the boolean difference calculus[C]∥26th IEEE Int’l Conf.on Computer Design.Lake Tahoe,2008:7-13
[28] Han J,Chen H.Reliability evaluation of logic circuits usingprobabilistic gate models[J].Microelectron Reliability,2011,51(2):468-476
[29] Singh N S S,Hamid N H,et al.Evaluation of circuit reliability based on distribution of different signal input patterns[C]∥8th IEEE Int’l Colloquium on Signal Processing and its Applications.Malacca,2012:5-9
[30] Asadi H,Tahoori M B,Tirumurti C.Estimating error propagation probabilities with bounded variances[C]∥22nd IEEE Int’l Symp.on Defect and Fault Tolerance in VLSI Systems.Rome,Italy,2007:41-49
[31] Zhu Xiao-wei,Baumann R,Pilch C,et al.Comparison of product failure rate to the component soft error rate in A muti-core di-gital signal processor[C]∥IEEE 43rd Annual International Relia-bility Physics Symposium.New York,2005:209-214
[32] Sierawski B D,Mendenhall M H,Reed R A,et al.Muon-induced single event upsets in deep-submicron technology [J].IEEE Trans.On Nuclear Science,2010,57(6):3273-3278
[33] Sierawski B D,Reed R A,Marcus M H,et al.Effects of Scaling on Muon-Induced Soft Errors[C]∥IEEE 49th Annual International Reliability Physics Symposium.Monterey,California,USA,2011:1-6
[34] Huang Hai-lin,Tang Zhi-min,Xu Tong.Fault Injection and Soft Error Sensitivity Characterization for Fault-Tolerant Godson-1 Processor[J].Journal of Computer Research and Development,2007,43(10):1820-1827(in Chinese) 黄海林,唐志敏,许彤.龙芯1号处理器的故障注入方法与软错误敏感性分析[J].计算机研究与发展,2007,3(10):1820-1827
[35] Gong Rui,Chen Wei,Liu Fang,et al.FT51:A Soft Error Tole-rant High Reliable Micro Controller[J].Chinese Journal of Computers,2007,30(10):1662-1673(in Chinese) 龚锐,陈微,刘芳,等.FT51:一种容软错误高可靠微控制器[J].计算机学报,2007,30(10):1662-1673
[36] Cristian C,Mike B,Chris W.Error Injection-based study of soft error propagation in AMD Bulldozer Microprocessor Module[C]∥Proceeding of International Conference on Dependable Systems and Networks.Boston,MA,USA,2012:1-6
[37] Mukherjee S S,Weaver C,Emer J,et al.A Systematic Metho-dology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor[C]∥Proc.IEEE/ACM Int’l Symp.on Microarchitecture(MICRO-36).Westin Horton Plaza San Diego,CA,2003:29-40
[38] Li Xiao-dong,Adve S V,Bose P,et al.Online Estimation of Architecture Vulnerability Factor for Soft Errors[C]∥Proc.of the 35th Int’l Symp on Conference of Computer Architecture(ISCA).Beijing,China,2008:341-352
[39] Mukherjee S S,Emer J,Reinhardt S K.The Soft Error Problem:An Architectural Perspective[C]∥Proc.of the 11th Int’l Symp.on High-Performance Computer Architecture.San Francisco,2005:243-247
[40] Xu Xin,Li M L.Understanding soft error propatation using efficient vulnerability-driven fault injection[C]∥Proceeding of International Conference on Dependable Systems and Networks.Boston,Massachusetts,USA,2012:1-12

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