Abstract: For modern microprocessors,the very long instruction word(VLIW) architecture integrating vector processing units has gradually become a typical representative of high-performance digital signal processor(DSP) architectures.This architecture is mainly characterized by rich register resources and many instruction execution units.Based on these characteristics,a selection method for the corresponding loop unrolling factor is proposed to improve the effect of loop unrolling optimization.This method takes into account the vector or scalar attribute of the code in a loop body,and the usage rules of base address registers and index registers.Moreover,another two heuristics,i.e.,the proportion of the times that the execution units are used and the power alignment of unrolling factor,are used in the loop unrolling factor selection algorithm.The ability of this method in developing more instruction level parallelism is proved by experiments performed on three commonly used digital signal processing algorithms.Experiment results show that the average performance of the algorithms improves by more than 10% compared with the existing methods.In particular,experiments on FFT algorithm show that the proposed method can analyze the usage of related hardware resources more accurately through the hybrid resource heuristics,and makes the judgment of unrolling and obtains the corresponding value of loop unrolling factor.

Key words: Compiler optimization, Loop unrolling, Unrolling factor, Vector DSP, VLIW