Computer Science ›› 2026, Vol. 53 ›› Issue (6): 163-170.doi: 10.11896/jsjkx.251000116

• High Performance Computing • Previous Articles     Next Articles

Optimizing SPMM on ARM Architectures with JIT Instruction Generation

SHI Jun, WANG Qinglin, TIAN Feiyang, WANG Zhicheng, LI Runhua, LIU Jie   

  1. Laboratory of Digitizing Software for Frontier Equipment,National University of Defense Technology,Changsha 410073,China
    National Key Laboratory of Parallel and Distributed Computing,National University of Defense Technology,Changsha 410073,China
    College of Computer Science and Technology,National University of Defense Technology,Changsha 410073,China
  • Received:2025-10-27 Revised:2025-12-22 Online:2026-06-15 Published:2026-06-09
  • About author:SHI Jun,born in 2000,MS candidate.His main research interests include high performance computing and parallel computing.
    WANG Qinglin,born in 1987,Ph.D,associate research fellow.His main research interests includes high perfor-mance computing and artificial intelligence.
  • Supported by:
    Optimization and Upgrading of the Tianhe High-Performance Computing System(2021YFB0300101).

Abstract: In recent years,with the rapid adoption of ARM architecture processors in edge computing devices and cloud servers,as well as the increasingly critical role of sparse matrix multiplication(SPMM)in compute-intensive applications such as deep learning,research on sparse computing optimization for ARM platforms has become an academic hotspot.However,current SPMM solutions for ARM platforms primarily employ the ahead-of-time(AOT)compilation model,where all compilation is completed before program execution.Nevertheless,AOT solutions for SPMM face three major limitations:unnecessary memory accesses,additional branch overhead,and redundant instructions.This paper proposes ASPJIT,a just-in-time(JIT)assembly code generation framework for ARM platforms,designed to accelerate SPMM computation on ARM multi-core CPUs.ASPJIT dynamically optimizes the computation sequence using a sparse judgment-based column-to-row algorithm,leveraging runtime sparse feature analysis to significantly improve instruction-level parallelism(ILP).Additionally,ASPJIT reduces memory access latency by employing a register allocation strategy to cache frequently accessed data and maximizes arithmetic throughput by carefully selecting SIMD instruction sets.A performance evaluation of ASPJIT is conducted and compared it with two AOT baselines.The first involves existing SPMM implementations compiled with automatic vectorization using the ARM gcc compiler.The second utilizes optimized SPMM routines provided by ARM Eigen.The results demonstrate that ASPJIT delivers average speedups of 3.8x and 5.6x,respectively.

Key words: Sparse matrix-matrix multiplication(SPMM), Ahead-of-time(AOT), Just-in-time(JIT), Single instruction multiple data(SIMD), ARM multi-core CPUs

CLC Number: 

  • TP391
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