Computer Science ›› 2015, Vol. 42 ›› Issue (1): 59-62.doi: 10.11896/j.issn.1002-137X.2015.01.013

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Implementation and Exploring of Acceleration Efficiency of Parallel AES Algorithm on CUDA

FEI Xiong-wei, LI Ken-li, YANG Wang-dong and DU Jia-yi   

  • Online:2018-11-14 Published:2018-11-14

Abstract: Many services of network applications need data encryption to provide secure communication especially for e-bank and e-business.Massive application servers are challenging for intense computation of unlimited encryption.CUDA (Compute Unified Device Architecture) is a platform for parallel and general-purpose computation on GPU(Graphics processing unit).It can improve the performance of encryption with existed graphics device resource in a low cost manner.A Parallel AES (Advanced Encryption Standard) algorithm is implemented on a Nvidia Geforce G210 graphics card and a serial AES algorithm is implemented on AMD Athlon 7850.This parallel AES algorithm avoids synchronization and communication between threads in a same block and improves performance of acceleration completely.The parallel AES algorithm’s performance model is explored in a enormous data(up to 32MB) environment.The parallel AES algorithm’s speedup is 2.66 to 3.34 times larger than Manavski’s AES-128 parallel algorithm.Acceleration performance of parallel AES algorithm was analyzed from the aspect of acceleration efficient for the first time.Speedup of parallel AES in a 16 cores GPU is up to 15.83 times accompanying a acceleration efficiency of 99.898%.

Key words: Compute unified device architecture,Advanced encryption standard,Parallel,Speedup ratio,Acceleration efficiency

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