Abstract: Multi-level cell (MLC) STT-RAM which can store multiple bits per cell,has been considered as a promising alternative to SRAM for the last-level Cache.MLC STT-RAM can reduce static power consumption significantly and has smaller cell size facilitates and better read performance.However,a major shortcoming of MLC STT-RAM Cache is its inefficient write operations.Based on hard/soft partition structure,this paper implemented write intensity prediction for energy-efficient MLC STT-RAM LLC.The objective of this architecture is to dynamically predict whether blocks will be written more than certain times thereby helping to reduce write latency and energy of MLC STT-RAM Cache.The key idea to solve this problem is to correlate write intensity with memory access instruction addresses.On top of that,this paper designed MLC STT-RAM LLC based on this predictor,in which prediction results are used to determine Cache line placement.Experimental results showed that this architecture reduces 6.3% of write energy consumption and improves system performance by 1.9% on average compared to the previous approach.

Key words: Energy-efficient, Last level high-speed cache, Multi-Level Cell Spin-Transfer Torque-RAM, Prediction mechanism