Abstract: Along with the development of device, process and application technology, chip multiprocessor is becoming the mainstream technology. As the scale of chip multiprocessor as well as the number of integrated on-chip cores is getting larger and larger, the network-on-chip, which is dedicated to the interconnection and communication among on-chip cores and other components, is becoming one of the performance bottlenecks of chip multiprocessor. hhe topology of network-on-chip defines the physical layouts and the interconnection patterns of network nodes,determines the cost,latency, throughput, area, fault tolerance and power of network-on-chip, and impacts on the network routing policies, theplacement and routing designs of network chips. Therefore, the topology is one of the key technologies of network-on-chips. The paper compared various topological structures of network-on-chips in brief , analyzed their performances, and proposed recommendations for future research on the topology of network-on-chip.

Key words: Chip multiprocessor, Network-on-chip, Topology, Pcrformance analysis