Abstract: As we known, the test of integrated circuits(IC) always encounters a lot of problems, like, processing the huge test data volume, spending a long time to test, and constructing the complex test structure. The paper proposed a serial shifter method for test generation based on extension scan chains. It is on basis of F八N algorithm and makes use of don't care bits `X' of test set. Scan chains can generate test vector by itself. Experiments were made for the whole scan chain and the segmentation. Results show that the proposed method can achieve less test data volume compared with some other classical method. The whole shift and the segmentation one arc prevailing in compression rate and test time respectively.

Key words: Test generation, Serial shifter, Segmentation shifter, Test data compression, Test application time