Abstract: The evaluation of speed and performance in hardware is very important with SHA-3 competition. And for one of the final round candidates-Skein algorithm, its 4-unrolled structure has short critical path and 8-unrolled structure used fewer multiplexers. So combining the advantages of the two structures, we proposed a pipeline design with two stages and implemented on Xilinx Virtex-5. Finally the experimental simulation shows that this approach can greatly increase the throughput of Skein algorithm.

Key words: SHA-3 , Skein, Pipeline, FPGA