Computer Science ›› 2009, Vol. 36 ›› Issue (4): 289-292.

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HAN Wei, JIANG Chuan (Microelectronic Center, CSIC Wuhan Digital Engineering Institute,Wuhan 430074,China)   

  • Online:2018-11-16 Published:2018-11-16

Abstract: The hidden logic flaw and circuit fault are most difficult situation in implementation of ASIC. A comprehensive DFT technique can implement active detection and path tracing in SOC circuit, according to various circuits characteristic. The technique inclu

Key words: SOC test, DFT (Design For Testability), Active test technique, Fault pattern, ATPG (Automatic Test Pattern Generation)

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