Computer Science ›› 2018, Vol. 45 ›› Issue (11A): 71-75.

• Review • Previous Articles     Next Articles

Age of Big Data:from Von Neumann to Computing Storage Fusion

QIU Ci-yun, LI Li, ZHANG Huan, WU Jia   

  1. Shanghai V&G Information System,Ltd,Shanghai 201702,China
  • Online:2019-02-26 Published:2019-02-26

Abstract: The emergence of massive data and improvement of computing power aroused the 3rd artificial intelligence booming,and the age of big data arrived.This paper firstly analyzed firstly that computer with Von Neumann architecture faces the problem of memory wall,bandwidth wall and high power consumption in the age of big data,which evokes the changing of computer architecture development trend to match the requirement of big data processing.Then,the computing and storage fusion in computer architecture level,software and hardware structure,spirit of offloading algorithm,technology feature background,and the commercial application were analyzed,to enlighten the product design such as high performance computing,data centre setup and design of smart SSD.In micro level,the 3D stack package technology based on through silicon via was analyzed and the latest industry applications were introduced.Finally,artificial cognitive computation which represents the computing and storage fusion development goal and the latest research status were summarized.

Key words: 3D stack, Computing and storage fusion, Memory wall, Near-data processing, Smart solid state drives

CLC Number: 

  • TP303
[1]WULF W A,MCKEE S A.Hitting the memory wall:Implications of the obvious[J].SIGARCH Computer Architecture News,1995,23(1):20-24.
[2]TIWARI D,VAZHKUDAI S,KIM Y,et al.Reducing data movement costs using energy efficient,active computation on SSD[C]∥USENIX Conference on Power-aware Computing & Systems.2012:4.
[3]ROGERS B M,KRISHNA A,BELL G B,et al.Scaling the bandwidth wall:Challenges in and avenues for CMP scaling[J].SIGARCH Computer Architecture News,2009,37(3):371-382.
[4]STANLEY-MARBELL P,CABEZAS V C,LUIJTEN R.Pinned to the walls:impact of packaging and application properties on the memory and power walls[C]∥2011 International Sympo-sium on Low Power Electronics and Design (ISLPED).2011:51-56.
[5]DENG Z X,XU C,CAI Q,et al.Reduced-Precision Memory Value Approximation for Deep Learning[Z].Hewlett Packard Labs,2015.
[6]RUSSELL J.Google Debuts TPU v2 and will Add to Google Cloud[EB/OL].https://www.hpcwire.com/ 2017/05/25/google-debuts-tpu-v2-will-add-google-cloud.
[7]STARKE W J,DALY D,BLANER B,et al.The cache and memory subsystems of the IBM POWER8 processor[J].IBM Journal of Research and Development,2015,59(1):1-3.
[8]JÜLICH SUPERCOMPUTING CENTRE.Blue Gene Active Storage Boosts I/O Performance at JSC[EB/OL].http://www.fz-juelich.de/sharedDocs/pressemitteilungen/UK/EN/2013/13-11-18bags.html.
[9]KGIL T,MUDGE T.FlashCache:A NAND flash memory file cache for low power web servers[C]∥International Conference on Compilers,Architecture,and Synthesis for Embedded Systems.2006:103-112.
[10]LEE B C,IPEK E,MUTLU O,et al.Architecting phase change memory as a scalable DRAM alternative[C]∥Proceedings of the 36th Annual International Symposium on Computer Architecture(ISCA’09).2009:2-13.
[11]Phase Change Memery[EB/OL].http://www.pdl.cmu.edu/SDI/2009/slides/Numonyx.pdf.
[12]CHEN X,XIAO N,LIU F.Survey on I/O Stack for New Non-Volatile Memory[J].Journal of Computer Research & Development,2014,51(Suppl.):18-24.
[13]谢源.人工智能时代的计算机架构创新[C/OL].新智元·AI WORLD 2017 世界人工智能大会.http://www.sohu.com/a/207987558_473283.
[14]CHI P,LI S C,XU C,et al.PRIME:A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory[C]∥ISCA.2016:27-39.
[15]李双辰,谢源.计算存储一体化芯片[J].中国计算机学会通讯,2018,14(2):16-19.
[16]SEBASTIAN A,TUMA T,PAPANDREOU N,et al.Temporal correlation detection using computational phase-change memory[J].Nature Communications,2017,8(1):1-10.
[17]SHAINER G.Intelligent networks:A new co-processor emerges
[EB/OL].The Next Platform,http://www.nextplatform. com/2016/03/02/intelligent-networks-a-new-co-processor-emerges.
[18]TRADER T.Mellanox touts arrival of intelligent interconnect
[EB/OL].https://www.hpcwire.com/?s=Mellanox+touts+arrival+of+intelligent+interconnect.
[19]WANG J G,PARK D,PAPAKONSTANTINOU Y,et al.SSD In-Storage Computing for Search Engines[J].IEEE Transactions on Computers,2016,PP(99):1.
[20]PARK D C,KEE Y S.In-Storage Computing for Hadoop Map-Reduce Framework:Challenges and Possibilities[J].IEEE Transactions on Computers,2016,PP(99):1.
[21]WANG J,PARK D,KEE Y S,et al.SSD In-Storage Computing for List Intersection[C]∥DaMoN.2016:1-8.
[22]DE A,GOKHALE M,GUPTA R,et al.Minerva:Accelerating data analysis in next-generation SSDs[C]∥IEEE International Symposium on Field-programmable Custom Computing Machines.2013:9-16.
[23]BAE D,KIM J,KIM S,et al.Intelligent SSD:A turbo for big data mining[J].Computer Science & Information Systems,2013,13:1573-1576.
[24]LEE Y S,QUERO L C,LE Y,et al.Accelerating external sorting via on-the-fly data merge in active SSDs[C]∥Usenix Conference on Hot Topics in Storage & File Systems.2014.
[25]SESHADRI S.Willow:A user-programmable SSD[C]∥Usenix Conference on Operating Systems Design Implementation.2014:67-80.
[26]KIM S,OH H,PARK C,et al.Fast energy efficient scan inside flash memory[C]∥Proceedings of 2nd International Workshop Accelerating Data Management Systems Using Modern Processor Storage Architecture.2011:36-43.
[27]DO J,KEE Y S,PATEL J M,et al.Query processing on smart SSDs:Opportunities and challenges[C]∥ACM Sigmod International Conference Management of Data.2013:1221-1230.
[28]WOODS L,ISTV_AN Z,ALONSO G.Ibex—An intelligent storage engine with support for advanced SQL off-loading[J].Proceedings of the VLDB Endowment,2014,7(11):963-974.
[29]OHMACHT M,GSCHWIND M,BOYLE P,et al.The IBM Blue Gene/Q Compute Chip[J].IEEE Micro,2012,32(2):48-60.
[30]TERADATA Corporation.TERADATA extreme performance alliance[EB/OL].http://www.teradata.com/t/extreme-performance-appliance.
[31]CHRISTMAN G,JERNIGAN K.Oracle exadata white paper[M].500 Oracle Parkway,Redwood shores,CA,Oracle Corporation,2011.
[32]翁楚良,张树杰.计算与存储融合体系结构[J].中国计算机学会通讯,2014,10(4):24-29.
[33]WILLIAMS S,WATERMAN A,PATTERSON D.Roofline:An insightful visual performance model for multi-core architectures[J].ACM,2009,52(4):65-76.
[34]PATTY C C.Wafer-scale Assembly & Heterogeneous Integration Technologies for MMICs [C]∥IMS 2012 3D Integrated Circuit Workshop.2016.
[35]KIM Y J,JOSHI Y K,FEDOROV A G,et al.Thermal characterization of interlayer microfluidic cooling of three-dimensional integrated circuits with nonuniform heat flux[J].Journal of Heat Transfer,2010,132(4):2.
[36]余山.从脑网络到人工智能——类脑计算的机遇与挑战[J].科技导报,2016,34(7):75-77.
[37]CHUA L O.Memristor:the missing circuit element[J].IEEE Transactions on Circuit Theory,1971,18(5):507-519.
[38]JO S H,CHANG T,EBONG I,et al.Nanoscale Memristor Device as Synapse in Neuromorphic Systems[J].Nano Letter,2010,10(4):1297-1301.
[39]STRUKOV D B,SNIDER G S,STEWART D R,et al.The missing memristor found[J].Nature,2008,453:80-83.
[40]THOMAS A.Memristor-based neural networks[J].Journal of Physics D Applied Physics,2013,46(9):093001.
[41]MEROLLA P A,ARTHUR J V,ALVARE-ICAZA R,et al.Artificial brains:A million spiking-neuron integrated circuit with a scalable communication network and interface[J].Scien-ce,2014,345:668-673.
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