计算机科学 ›› 2014, Vol. 41 ›› Issue (5): 37-40.doi: 10.11896/j.issn.1002-137X.2014.05.008
张双悦,李硕,王红,杨士元
ZHANG Shuang-yue,LI Shuo,WANG Hong and YANG Shi-yuan
摘要： 基于内建自测试(BIST)思想的FPGA测试方法利用被测芯片中的资源来构建测试所需的TPG或ORA,以减少测试对输入输出引脚和外部ATE的需求。传统的FPGA芯片BIST方法仅考虑自测试结构内被配置为CUT的资源,从而需要进行多次组测试来完成整个芯片的测试。在现有LUT自测试链结构的基础上,通过合理选择TPG的电路结构及测试配置,能够在相同测试开销下增加TPG部分的故障覆盖率,提高测试效率。
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