Computer Science ›› 2014, Vol. 41 ›› Issue (5): 37-40.doi: 10.11896/j.issn.1002-137X.2014.05.008
Previous Articles Next Articles
ZHANG Shuang-yue,LI Shuo,WANG Hong and YANG Shi-yuan
| [1] Wei K H,Meyer F J,Xiao-Tao C,et al．Testing configurable LUT-based FPGA’s[J]．IEEE Trans．on Very Large Scale Integration (VLSI) Systems,1998,6(2):276-283 [2] Wei K H,Meyer F J,Lombardi F．An approach for detecting multiple faulty FPGA logic blocks[J]．IEEE Trans．on Compu-ters,2000,49(1):48-54 [3] Abramovici M,Stroud C E．BIST-based test and diagnosis ofFPGA logic blocks[J]． IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2001,9(1):159-172 [4] Atoofian E,Navabi Z．A BIST architecture for FPGA look up table testing reduces reconfigurations[C]∥12th Asian Test Symp(ATS)．2003:84-89 [5] Alaghi A,SadoughiYarandi M,Navabi Z．An Optimum ORABIST for Multiple Fault FPGA Look-Up Table Testing[C]∥Test Symposium,2006(ATS’ 06)．15th Asian．2006 [6] Nandha Kumar T,Chong C W．An automated approach for locating multiple faulty LUTs in an FPGA[J]．Microelectronics Reliability,2008,48(11):1900-1906 [7] Chun-Lung H,Ting-Hsuan C．Built-in Self-Test Design forFault Detection and Fault Diagnosis in SRAM-Based FPGA[J]．IEEE Trans．on Instrumentation and Measurement,2009,58(7):2300-2315 [8] Abramovici M,Stroud C．BIST-based detection and diagnosis of multiple faultsin FPGAs[C]∥Proceedings of the IEEE International Test Conference．2000 [9] Harris I G,Tessier R．Testing and diagnosis of interconnectfaults in cluster-based FPGA architectures[J]．IEEE Trans．on Computer-Aided Design of Integrated Circuits and Systems,2002,21(11):1337-1343 [10] Huang W,et al．Testing memory modules in SRAM-based configurable FPGAs[C]∥ Proceedings,International Workshop on Memory Technology,Design and Testing,1997．1997 |
| No related articles found! |
|
||
Home