计算机科学 ›› 2023, Vol. 50 ›› Issue (12): 66-74.doi: 10.11896/jsjkx.230100030
高轩, 何港兴, 车文博, 扈啸
GAO Xuan, HE Gangxing, CHE Wenbo, HU Xiao
摘要: 软件调试是嵌入式系统开发中最具挑战性的难点之一。在进行高复杂性、高实时性系统调试时,单步-断点时间开销大,易破坏程序执行行为;采用串接机制的JTAG接口,在实现对处于工作状态的复杂多核处理器的并行访问时存在缺陷。片上追踪调试技术通过专用硬件非侵入地获取程序执行状态,有效解决了上述问题。现有的片上追踪调试技术相关研究以追踪完整信息为主,易产生大量无意义的数据;此外,也未考虑压缩后的数据在窄总线上的传输问题。文中设计并实现了一种基于RISC-V指令集的面向多核微处理器的非侵入式追踪调试系统RVTDS,通过复用RISC-V核内平台级别中断控制器,解决多核微处理器高速并行调试时的数据丢失问题;提出了面向片上总线的数据流追踪方案和基于指令位域匹配的控制流过滤机制以实现信息筛选,提供总线带宽统计功能;提出了基于差分编码的数据压缩方法,数据平均压缩率达82%以上;提出了一种数据打包方案以实现窄总线上的数据传输问题,每拍有效数据平均可容纳约1.5个路径信息。系统验证结果表明,RVTDS与传统片上追踪调试方法相比,追踪数据量小,可以灵活高效地完成复杂多核微处理器多种片内运行信息的采集、传输和存储。
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[1]ALABOUDI A,LATOZA T D.An Exploratory Study of De-bugging Episodes[J].arXiv.2105.02162,2021. [2]POUGOTI M,MILENKOVIC A.Enabling On-the-Fly Hard-ware Tracing of Data Reads in Multicores[J].ACM Transactions on Embedded Computing Systems.2019,18(4):1-27. [3]BI R,HU H.A Non-Intrusive Real-time Debugging Method for Programs:CN107315685A[P].2017. [4]JTAG Technologies.When does boundary-scan make sense[EB/OL].https://www.jtag.com/white-paper/when-does-boundary-scan-make-sense/. [5]THOMAS B P,SMITHA G,ABHI D R.Everything You Al-ways Wanted to Know About Embedded Trace[J].Computer,2022,55(2):34-43. [6]HU X L,JIN Y,LI Z L.A Parallel JTAG-based Debugging and Selection Scheme for Multi-core Digital Signal Processors[C]//2018 IEEE International Conference of Safety Produce Informatization(IICSPI).2018:527-530. [7]HSIEH M C,HUANG C T.An embedded infrastructure of debug and trace interface for the DSP platform[C]//IEEE Design Automation Conference.2008. [8]DUAN H X,YU L X,ZHOU H Y,et al.An On-Chip AHB Bus Tracer for Non-intrusive Debugging[C]//2019 IEEE 3rd Advanced Information Management,Communicates,Electronic and Automation Control Conference(IMCEC).2019:322-326. [9]DUAN H X,YU L X,ZHOU H Y,et al.An Embedded Tracing Debug Implementation for Crossbar Type Bus in Muti-core SoC[C]//2020 IEEE 3rd International Conference on Electronics Technology(ICET).2020:63-67. [10]RAMIREZ W,ROA E.Post-Silicon Debugging Platform with Bus Monitoring Capability to Perform Behavioral and Perfor-mance Analyses[C]//2019 IEEE 10th Latin American Symposium on Circuits & Systems(LASCAS).2019:81-84. [11]WANGER P,WILD T,HERKERSDORF A.DiaSys:On-Chip Trace Analysis for Multi-processor System-on-Chip[C]//International Conference on Architecture of Computing Systems.2016. [12]CHENG Y,LIH W,SHEN H H,et al.On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2018,37(10):2166-2179. [13]CAO Y T,ZHENG H,RAY S.A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration Debug[C]//20th Inter-national Symposium on Quality Electronic Design(ISQED).2019:278-283. [14]XIAO W Y,ZHENG L X.Adaptive Huffman Coding Systemand Method:CN114900193A[P].2022-08-12. [15]CHUNG-FU K,SHYH-MING H,ING-JER H.A HardwareApproach to Real-Time Program Trace Compression for Embedded Processors[J].IEEE Transactions on Circuits & Systems,2007,54(3):530-543. [16]FU-CHING Y,YI-TING L,CHUNG-FU K,et al.An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC[J].IEEE Transactions on Very Large Scale Integration Systems,2011,19(4):571-584. [17]ROUT S S,DEB S,BASU K.Wind:An efficient post-silicon debug strategy for network on chip[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2020,40(11):2372-2385. [18]OH H,CHOI I,KANG S.DRAM-Based Error Detection Me-thod to Reduce the Post-Silicon Debug Time for Multiple Identical Cores[J].IEEE Transactions on Computers,2017,66(9):1504-1517. |
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