计算机科学 ›› 2007, Vol. 34 ›› Issue (11): 259-263.

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多核处理器降低功耗技术综述

  

  • 出版日期:2018-11-16 发布日期:2018-11-16
  • 基金资助:
    国家自然科学基金(No.60503090)、北京市自然科学基金(No.4042,081)、973子项目(No.2004CB217903).

  • Online:2018-11-16 Published:2018-11-16

摘要: 随着芯片集成度越来越高,处理器功耗已经和性能、时钟频率、芯片尺寸共同成为衡量一个处理器优劣的最主要标准。传统的降低功耗的技术都是针对功耗本身,即动态消耗和静态消耗,针对动态消耗的有多元供能电压技术(Multiple Supply Voltage)、动态电压调节技术(Dynamic Voltage Scaling)和基于时钟信号的技术,针对静态消耗的有通道长度调整技术(Channel Length Scaling)、寄存器锁存技术和能量选通技术(Power Gating)。近两年从处理器结构和算法角度思考降

关键词: 动态消耗 静态消耗 结构和算法优化

Abstract: With the increasing in chip density, power consumption, together with performance, clock rate and chip area, has become the prime criterions to evaluate a processor. Traditional technologies mostly focus on the consumption itself including dynamic and sta

Key words: Dynamic consumption, Static consumption, Architecture and algorithm optimization

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