计算机科学 ›› 2008, Vol. 35 ›› Issue (8): 74-76.

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基于FPGA的TOE系统设计与实现

王圣 苏金树   

  1. 国防科大计算机学院,长沙410073
  • 出版日期:2018-11-16 发布日期:2018-11-16
  • 基金资助:
    获国家自然科学基金资助,项目编号为90604006.

WANG Sheng SU Jin-shu (Computer School, NUDT, Changsha 410073, China)   

  • Online:2018-11-16 Published:2018-11-16

摘要: 随着网络带宽的迅速增长,主机协议处理开销已经成为系统整体性能的瓶颈。为了有效增加系统吞吐率,进一步减轻CPU的负担,本文详细描述了一种基于FPGA(Field Programmable Gate Array)的TOE(TCP Offload Engine)系统的设计与实现。实验结果表明,系统在吞吐率等方面明显优于非TOE系统。

关键词: FPGA TOE 设计

Abstract: With the rapid increment of network bandwidth, the overheads of protocol on host have become the bottleneck of system performance. To increase the throughput efficiently and alleviate the burden of CPU,we design and implement a system based on FPGA (Field

Key words: FPGA, TOE, Design

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