计算机科学 ›› 2012, Vol. 39 ›› Issue (1): 65-68.
• 计算机网络与信息安全 • 上一篇 下一篇
闫丁丽,刘航,郭达伟,李杨,洪亮
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摘要: 硬件实现的速度和性能是SHA-3算法甄选的重要指标。针对SHA-3末轮5个候选算法之一的Skein算法,结合其4轮迭代结构的关键路径较短而8轮迭代结构实现所用的选择器较少的优点,采用FPGA实现了一个两级流水线结构的Skein算法IP核。仿真验证结果表明,该算法在Xilinx Virtex-5上数据吞吐量达到6. 4Gbps,比之前的非流水线结构速度性能提高了82%以上,硬件资源利用率提高了2100,特别适用于Hash树计算。
关键词: SHA-3 , Skein,流水线,FPGA
Abstract: The evaluation of speed and performance in hardware is very important with SHA-3 competition. And for one of the final round candidates-Skein algorithm, its 4-unrolled structure has short critical path and 8-unrolled structure used fewer multiplexers. So combining the advantages of the two structures, we proposed a pipeline design with two stages and implemented on Xilinx Virtex-5. Finally the experimental simulation shows that this approach can greatly increase the throughput of Skein algorithm.
Key words: SHA-3 , Skein, Pipeline, FPGA
闫丁丽,刘航,郭达伟,李杨,洪亮. Skein算法的流水线结构设计与实现[J]. 计算机科学, 2012, 39(1): 65-68. https://doi.org/
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