摘要: 混合主存储器由DRAM构成,它可用作cache来扩展非易失性存储器,相比传统的主存储器能够提供更大的存储能力。不过,要使混合存储器具有高性能和可扩展性,一个关键的挑战在于需要对缓存在DRAM中的数据的元数据(如标签)以一个细粒度的方式进行有效管理。基于这样的观察:利用DRAM缓存行的局部性,将元数据与元数据对应的数据存储在片外缓存中相同的行,使用一个小的缓冲区来只缓存最近被访问的片内缓存行,以降低细粒度DRAM缓存的开销。利用这种细粒度的DRAM高速缓存的灵活性和效率,还开发了一种自适应的策略来选择在数据迁移到DRAM时最佳的迁移粒度。在搭配了512MB的DRAM缓存的混合型存储系统中,建议使用8kB的片上缓存,这样,相比一个传统的8MB的SRAM元数据存储,即使没有考虑大的SRAM元数据存储的能源开销,也可以提升6%以内的性能,以及18%的能效节约。
[1] Lee B C,Ipek E,Mutlu O,et al.Architecting phase changememory as a scalable DRAM alternative[C]∥Proceedings of ISCA ’09.2009:171-182 [2] Qureshi M K,Srinivasan V,Rivers J A.Scalable high perfor-mance main memory system using phase-change memory techno-logy[C]∥Proceedings of ISCA’09.2009:101-112 [3] Dong X,Xie Y,Muralimanohar N,et al.Simple but effectiveheterogeneous main memory with on-chip memory controller support[C]∥Proceedings of SC’10.2010:773-778 [4] Zhao L,Iyer R,Illikkal R,et al.Exploring DRAM cache architectures for CMP server platforms[C]∥Proceedings of ICCD’07.2007:253-259 [5] Loh G,Hill M D.Efficiently enabling conventional block sizes for very large die-stacked DRAM caches[C]∥Proceedings of MICRO’11.2011:123-128 [6] Rixner S,Dally W J,Kapasi U J,et al.Memory access scheduling[C]∥Proceedings of ISCA’00.2000:58-69 [7] Zuravleff W K,Robinson T.Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order[P].U.S.patent 5630096.1997 [8] Eyerman S,Eeckhout L.System-level performance metrics for multiprogram workloads[C]∥Proceedings of MICRO’08.2008:147-158 [9] Qureshi M K,Lynch D N,Mutlu O,et al.A case for MLP-aware cache replacement[C]∥Proceedings of ISCA’06.2006:211-221 [10] Jiang X,Madan N,Zhao L,et al.CHOP:Adaptive filter-basedDRAM caching for CMP server platforms[C]∥Proceedings of HPCA’10.2010:165-175 [11] Liptay J.Structural aspects of the System/360Model 85,II:The cache[J].IBM Syst.J.,1968,7(1):15-21 [12] Seznec A.Decoupled sectored caches:conciliating low tag implementation cost and low miss ratio[C]∥Proceedings of ISCA’94.1994:19-28 [13] Wang H,Sun T,Yang Q.CAT-caching address tags-a technique for reducing area cost of on-chip caches[C]∥Proceedings of ISCA’95.1995:188-196 [14] Inoue K,Kai K,Murakami K.Dynamically variable linesizecache exploiting high on-chip memory bandwidth of merged DRAM/logic LSIs[C]∥Proceedings of HPCA’99.1999:119-128 [15] Johnson T L,Hwu W-M W.Run-TIRDe adaptive cache hierarchy management via reference analysis[C]∥Proceedings of ISCA’97.1997:134-145 [16] Mandelman J A,Dennard R H,Bronner G B,et al.Challengesand future directions for the scaling of dynamic random-access memory (DRAM)[J].IBM J.Res.Dev.,2002,46(2/3):187-212 |
No related articles found! |
|