计算机科学 ›› 2020, Vol. 47 ›› Issue (4): 42-49.doi: 10.11896/jsjkx.190300088
程煜1, 刘伟1,2,3, 孙童心1, 魏志刚1, 杜薇1,2
CHENG Yu1, LIU Wei1,2,3, SUN Tong-xin1, WEI Zhi-gang1, DU Wei1,2
摘要： 随着硅的集成度和时钟频率的急剧提升,功耗和散热已成为体系结构设计中的关键挑战。近阈值电压技术是一种能够有效降低处理器能耗的有着广泛应用前景的技术。然而,在近阈值电压下,大量SRAM单元失效,导致一级缓存的错误率升升,给一级缓存的可靠性带来了严峻挑战。目前有很多学者通过牺牲缓存容量或者引入额外的延迟来纠正缓存的错误,但大多方法只能适应SRAM单元的低失效率环境,在高失效率的环境下表现较差。文中提出了一种基于传统6T SRAM的近阈值电压下可容错的一级缓存结构——FTFLC(Fault-Tolerant First-Level Cache),在高失效率的环境下,其表现出了更好的性能。FTFLC采用两级映射机制,利用块映射机制和位纠正机制分别对缓存行中有错的比特位和子数据块进行映射保护。此外,文中还提出了FTFLC初始化算法将两种映射机制结合,提高了可用的缓存容量。最后,使用gem5模拟器,在650mV电压的高失效率环境下对FTFLC进行仿真实验,将其与3种已有缓存结构10T-Cache,Bit-fix,Correction Prediction进行对比。对比结果表明,FTFLC相比其他的缓存结构,在保持较低面积和能耗开销的同时,拥有至少3.86%的性能提升,且将L1 Cache的容量可用率提升了12.5%。
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