Abstract: With the aggressive silicon integration and clock frequency increasing,power consumption and heat dissipation have become key challenges in the design of high-performance processors.NTC is emerging as a promising solution to achieve an order of magnitude reduction in energy consumption in future processors.However,reducing the supply voltage to near-threshold level significantly increases the SRAM bit-cell failures,leading to the high error rate in L1 cache.Researchers have proposed techniques either by sacrificing capacity or incurring additional latency to correct the errors in L1 cache.But most schemes can only adapt to the low error rate environment of SRAM bit-cell,and perform poorly in high error rate environment.In this paper,this paper proposed a fault-tolerant First-Level Cache design (FTFLC) based on conventional 6T SRAM cells to solve reliability challenges in high error rate environment.FTFLC adopts a two-level mapping mechanism,which uses block mapping mechanism and bit correction mechanism to protect the faulty bits data in the cache line.In addition,this paper proposed a FTFLC initialization algorithm to improve the available cache capacity by combining two mapping mechanisms.Experimental results show that compared with three existing schemes,FTFLC improves performance by 3.86% and increases 12.5% L1 cache capacity while maintaining a low area and energy consumption.

Key words: Fault-tolerance, L1 cache, Low energy consumption, Near-threshold voltage, Reliability