Computer Science ›› 2014, Vol. 41 ›› Issue (7): 36-39.doi: 10.11896/j.issn.1002-137X.2014.07.006
Previous Articles Next Articles
FANG Juan,WANG Shuai and YU Lu
| [1] Herrero E,Gonz′alez J,Canal R．Distributed cooperative caching[C]∥Proceedings of the 17th International Conference on Pa-rallel Architectures and Compilation Techniques．2008:134-143 [2] Kotera I．Power-Aware Dynamic Cache Partitioning for CMPs H[C]∥Transactions on High-Performance Embedded Architectures and Compilers III．2011:135-153 [3] Sinharoy B,KallaR N,Tendler J M．Power 5system micro-architecture[M]．IBM J.Res Dev,2005,9:505-521 [4] Kim S,Chandra D,Solihin Y．Fair Cache sharing and partitioning in a chip multiprocessor architecture[C]∥Proc.of PACT 2004.Antibes,Juanles-Pins,France,2004:111-122 [5] Sui Xiu-feng,Wu Jun-min,Chen Guo-liang,et al.AugmentingCache Partitioning with Thread-Aware InsertionIPromotion Policies to Manage Shared Caches[C]∥Proceedings of the 7th ACM International Conference on Computing Frontiers.2004:79-80 [6] Meng Y,Sherwood T,Kastner．Exploring the limits of leakage power reduction in Caches[J]．ACM Trans．Archit．Code Optim．,2005,2:221-246 [7] Janapsatya A,Parameswaran S,Ignjatovic A．HitME:Low power Hit MEmory buffer for embedded systems[C]∥Asia and South Pacific Design Automation Conference．2009:335-340 [8] Tsai Y-Y,Chen C-H．Energy-Efficient Trace Reuse Cache forEmbedded Processors[J]．IEEE Transaction On Very Large Scale Integration(VLSI)System,2010,19:1681-1694 [9] Datta K A M A S．Energy efficient i-Cache using multiple line buffers with prediction[J]．IET Comput．Digit．Tech.,2008,2(5):355-362 [10] Ali K,Aboelaze M．Energy efficient I-Cache using multiple line buffers with prediction[J]．Computers and Digital Techniques,IET,2008(2):355-362 [11] Inoue K．Way-Predicting Set-Associative Cache for High Per-formance and Low Energy Consumption[C]∥Proceedings．1999International Symposium on Low Power Electronics and Design 1999(Cat．No.99TH8477)．1999:273-275 [12] Suo Guang,Yang Xue-jun,Liu Guang-hui,et al．IPC-BasedCache Partitioning:An IPC-Orient Dynamic Shared Cache [C]∥International Conference on Convergence and Hybrid Information Technology．Washington DC:IEEE Computer Society,2008:399-406 [13] Kim S,Chandra D,Solin Y.Fair Cache sharing and partitioning in a chip multiprocessor architecture[C]∥Proc．of PDCT 2004.Antibes,Juanles-PINS,France IEEE,2004:111-122 [14] Zhang C,Yang J,Vahid F．Low static-power frequent-value data Caches[C]∥The Design,Automation and Test in Europe Conference and Exhibition．Paris,France,2004,1:214-219 [15] Qureshi M K,Patt Y N．Utility based Cache partitioning:a low overhead,high performance,runtime mechanism to partition shared Caches[C]∥Proc.of the 39th Annual IEEE/ACM Int Symp on Microarchitecture.Orlando．Florida,USA:IEEE,2006:423-432 [16] Kobayashi H,Kotera I,Takizawa H.Locality analysis to control dynamicallyway-adaptable Caches[J]．SIGARCH Comput．Archit．News,2005,33(3):25-32 [17] Kobayashi H,Kotera I,Takizawa H．Locality analysis to control dynamically way-adaptable Caches[J]．SIGARCH Comput．Archit．News,2005,3:25-32 [18] Christensson M,Eskilson．Simics:a full system simulation platform[J]．IEEE Computer,2002(3):50-58 |
| No related articles found! |
|
||
Home