Abstract: To achieve the data error control in high-speed converged network data transmission,a nested CRC code ge-neration method was proposed to improve the situation that it is difficult to further enhance the computing speed through currently available cyclic redundancy check(CRC) code calculation technique．It was implemented on Xilinx Field Programmable Gate Array (FPGA) chip．This nested CRC code is obtained through calculating the traditional CRC code concurrently in multiple channels,and thus the speed of error control code generation is highly increased while multiple-types of data flows are processed by different kinds of calculating channels．At the end,the calculating performance and error control capability were analyzed and a guidance to set the nested level,the number of computing channel and parallel computing width of a single computing channel was given.

Key words: High-speed data transmission,Nested CRC code,Parallel calculator,Multiple channels,Multiple-types data flows