Abstract: Exposing and exploiting instruction-level parallelism (ILP) is one of the most critical components of high performance for modern processors. Wide-issue superscalar, very long instruction word (VLIW) and dataflow processors can only achieve high performance when they execute nearby instructions in parallel. In order to expose more instruction-level parallelism to hardware execution substrate, this paper proposed an improved fanout tree generation algorithm. This algorithm first calculates the priority value of every target instruction based on its execution probability and the critical path length from the target instruction to an exit of its block, and then sorts the priority values in ascending order and generates a software fanout tree. Experimental results show that the algorithm proposed in this paper improves the performance over the prior work modestly.

Key words: Software fanout free, Execution probability, Critical path, Priority