Abstract: Memory system becomes a bottleneck for the overall computer system performance. This paper reduced the average memory access latency using the characteristics of DRAM. Firstly, the control strategy for memory row buffer was studied. Secondly,a Read and Write Separated Predictor (RWS) for page mode prediction was proposed,a two saturated counter and a two level predictor to realize RWS were also proposed. Finally, a simulation platform based on SimpleScalar was constructed to evaluate the proposed predictors. The result shows that compared with CLOSE strategy, the average memory access latency is reduced about 26%, the average IPC speedup is about 4. 3 %. It is also shown that the average memory access latency is reduced about 19. 6%，the average IPC speedup is about 2. 5% Compared with OPEN strategy.

Key words: Memory system, Row buffer, Page mode prediction, Separated read and write