Abstract: Sparse matrix computations present additional challenges for harnessing the potential of modern graphics processing unit(GPU) for general-purpose computing. We investigated various optimizations on thread-mapping, data reuse etc. and a parallel Sparse Matrix-Vector multiplication(SpMV) on GPU with compute unified device architecture(CUDA) was proposed under compressed sparse row(CSR) structure afterwards. The optimizations include; (1) exploiting each clement using half-warp threads, which synchronize free within one warp; (2) making up integer address to achieve coalesced accesses; (3) data reuse through reading from texture vector resides in; (4) data transfer using page locked memory; (5) reading results in shared memory. We compared the performance of our approach with that of efficicnt parallel SpMV implementations such as(1)the one from NVIDIA’s CUDPP library and(2)the one from NVIDIA's SpMV library. Our approach outperforms two both in memory bandwidth and GFLOPS. In addition, the total performance of our approach is three times greater than that of a CPU counterpart.

Key words: Sparse matrix, Compressed sparse row, Graphics processing unit, Compute unified device architecture, Optimizations