Abstract: A novel architecture based on lifting wavelet transform was proposed to implementing CCSDS image compression algorithm on FPGA. The lincbased parallel architecture which consists of two row processors performs 3 level 2-D 9/7 integer to integer forward discrete wavelet transform and can process the 2 row image data simultaneously. The row and column data arc processed in parallel way by storing the middle data in the 10 row buffer. The whole 3 level wavelet transform architecture is optimized in the pipeline design way and achieve lower utilization and less storage time. The architecture which has been demonstrated on Altera Stratix II FPGA performs a decomposition in approximutely Nz/ 2 clock cycles for an NX N gray image. According to the experimental results,the new architecture can implement the wavelet transform for 1024X1024 gray image at 100 frame per-second and working at 86. SMHz.

Key words: 2-D 31eve1 discrete wavelet transform(DWT) , FPGA, CCSDS, Image processing, Parallel array