Abstract: Translation Look-Aside Buffer(TLB) is a dedicated hardware component that the Memory Management Unit(MMI)utilizes to improve page address tanslation speed. However, some researchers indicate that working TLBs may occupy as much as 17% of a processor's total power consumption. The o均ective of this paper is to effectively reduce the TLB on-chip power consumption by looking into the program behavior in respect of page access traits. With careful analysis of the memory access patterns of SPEC CPU benchmarks,we demonstrated that the Page Interval which non-sequential page accesses heavily exhibit can be used to largely reduce the power of TI_Bs. Based on this observation, we proposed a novel low-power hLB design methodology. Experimental results show that using our design the on-chip power consumption can be further saved.

Key words: Translation look-aside buffer(TLB) , Low power, Non-sequential accesses, Page interval