Abstract: Fault tolerant technique for reconfigurable multiprocessor array deals with the issue of reconstruction of the processor array which contains fault units to get the largest available target array. Previous research focused primarily on the reconfiguration algorithm, which does not involve in the study of the synchronous communication performance for reconstructed target array. This paper proposed an optimization algorithm which can improve the performance of the synchronous communication on target array as it reduces the communication delay between neighboring rows for the target array. Experimental results show that the proposed algorithm achieves improvement on communication synchro- nous performance on processor arrays with different scales and different fault densities.

Key words: VLSI array, Reconfiguration algorithm, Fault-tolerance, Synchronous optimization algorithm