Abstract: In order to accelerate the systems, High Level Synthesis(HLS) aims to map the computation of the system to the reconfigurable hardware, based on the behavioral description of the system in high level programming language. In HLS, the generation of efficient memory subsystem is critically important, especially for data intensive computation. In this paper, the existing HLS technologies for FPGA and their memory subsystems were analyzed. The generated memory subsystems' architectures were divided into three categories; DSP-like architecture, CPU-control architecture and architecture based on the reconfigurable memory functional units. These architectures were discussed with examples. Afto that, the front end and back end optimization techniques for memory subsystems in HI_S were discussed respectively. In addition, the aforementioned architectures and techniques were analyzed and evaluated. Finally, the mapping between the off-chip and on-chip memories and the efficient modeling for the programs were listed as the remained problems. In HI_S,syntheses for multi-module and automatic generation of the memory organization can be future research directions.

Key words: High level synthesis,FPGA,Memory subsystems,Reconfigurable architecture