Computer Science ›› 2013, Vol. 40 ›› Issue (12): 15-18.

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Design of Quadruple Precision Floating-point Fused Multiply-Add Unit Based on SIMD Device

HE Jun,HUANG Yong-qin and ZHU Ying   

  • Online:2018-11-16 Published:2018-11-16

Abstract: It is an important issue to resolve to decrease the hardware cost and operation latency for the implementation of quadruple precision floating-point arithmetic.To decrease the hardware cost of floating-point quadruple fused multiply add (QPFMA) unit,a new QPFMA unit was designed and realized based on a SIMD device,which supports 64bit×4double precision floating-point fused multiply add (DPFMA).The new QPFMA supports four kinds of FMA operation,multiplication,addition,subtraction and comparison,with the operation latency of 7cycles.By decomposing the 113bit×113bit multiplication of quadruple precision fraction into four 57bit×57bit multiplications to share the 53bit×53bit multipliers of SIMD DPFMA,the hardware cost of the new QPFMA is reduced greatly.Using the 65nm cell library,the new QPFMA is synthesized.The results show its frequency is 1.1GHz and area is 42.71% of a normal QPFMA unit,only equal to the area of a DPFMA unit.Comparing to current QPFMA design,the operation latency decreases by 3cycles and the gate number reduces by 65.96% in equivalent technology and at comparative frequency.

Key words: Floating-point,SIMD device,Fused multiply-add,Quadruple precision,High precision

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