Abstract: This paper presented the architecture of real-valued symmetric matrix eigenvalue decomposition based on rotation mode CORDIC algorithm on FPGA．The proposed architecture adopts a direct mapping by 32floating-point CORDIC-based process units that can compute the eigenvalue decomposition for a 3*3real symmetric matrix．In order to achieve a comprehensive resource and performance evaluation,the whole design was realized on Spartan-3xc3sd1800a-5FPGA．The evaluation results show that 1) the proposed architecture satisfies 3*3eigenvalue decomposition for the 2－20accuracy requirement when the word length of the data path is 32-bit; 2) occupies about 2467(14%) slices,and the maximum frequency is 154MHz．

Key words: Eigenvalue decomposition,CORDIC,FPGA,Floating data