Computer Science ›› 2018, Vol. 45 ›› Issue (6A): 562-567.

• Interdiscipline & Application • Previous Articles     Next Articles

Optimization of Register Allocation Strategy for MLC STT-RAM

NI Yuan-hui1,CHEN Wei-wen1,WANG Lei1,QIU Ke-ni1,2   

  1. College of Information Engineering,Capital Normal University,Beijing 100048,China1
    Beijing Advanced Innovation Center for Imaging Technology,Beijing 100048,China2
  • Online:2018-06-20 Published:2018-08-03

Abstract: Multi-level cell spin-transfer torque random access memory (MLC STT-RAM) is a promising nonvolatile memory technology.Unlike the SRAM that uses a charge mode to store information,MLC STT-RAM uses the spin polarization current to change the magnetic layer direction of the free layer through the magnetic tunneling junction (MTJ) to store information,so it can naturally avoid electromagnetic interference.This paper used the anti-electromagnetic radiation characteristics of MLC STT-RAM,and explored it as a register for its natural immunity to electromagnetic radiation in rad-hard space environment.MLC STT-RAM exhibits unbalanced write-state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped.This feature leads to nonuniform costs of write-states in terms of latency and energy.However,current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write-state transition costs.As a result,those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM.Aiming to address this li-mitation,this paper proposed a state-transition aware spilling cost minimization (SSCM) policy to save power when MLC STT-RAM is employed in register design.Specifically,the spilling cost model is first constructed according to the linear combination of different state transition frequencies.Directed by the proposed cost model,the compiler picks up spilling candidates with the highest cost to achieve lower power and higher performance.

Key words: MLC STT-RAM, Write-state transition, Potential spilling, Register allocation

CLC Number: 

  • TP336
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