计算机科学 ›› 2020, Vol. 47 ›› Issue (8): 127-131.doi: 10.11896/jsjkx.200600112

所属专题: 高性能计算

• 高性能计算 • 上一篇    下一篇

二进制域上椭圆曲线密码ECC的高性能FPGA实现

尤文珠, 葛海波   

  1. 西安邮电大学电子工程学院 西安 710121
  • 出版日期:2020-08-15 发布日期:2020-08-10
  • 通讯作者: 葛海波(gehaibo2417@aliyun.com)
  • 基金资助:
    陕西省自然科学基金(2011JM8038);陕西省重点产业创新链(群)项目(S2019-YF-ZDCXL-ZDLGY-0098)

High-performance FPGA Implementation of Elliptic Curve ECC on Binary Domain

YOU Wen-zhu, GE Hai-bo   

  1. School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China
  • Online:2020-08-15 Published:2020-08-10
  • About author:YOU Wen-zhu, born in 1995, postgradua-te.Her main research interests include security of internet of things and so on.
    GE Hai-bo, born in 1963, master, professor, master supervisor.His main research interests include optics and internet of things.
  • Supported by:
    This work was supported by the Natural Science Foundation of Shaanxi Province(2011JM8038) and Shaanxi Provincial Key Industry Innovation Chain(Group) Project(S2019-YF-ZDCXL-ZDLGY-0098).

摘要: 近年来, 通信领域得到了巨大的发展, 网上银行、移动通信等应用增加了资源受限环境下的安全需求。与传统密码算法相比, 椭圆曲线密码体制(Elliptic curve cryptography, ECC)提供了更好的安全标准, 为优化性能参数提供了更大的空间。为此, 文中提出了一种高效的椭圆曲线密码硬件设计方案。该方案在已有研究的基础上, 利用投影坐标系LD Montgomery阶梯算法对ECC中最核心的标量乘运算进行了研究, 并对群运算层采用并行调度来缩短延迟;对于有限域运算, 采用位并行乘法算法和改进的Euclidean求逆算法来实现;基于Xilinx Virtex-5和Virtex-7FPGA器件, 在二进制域域长分别为163, 233和283时实现了该体系结构。实验结果表明, 该方案所需现场可编程门阵列(Field-Programmable Gate Array, FPGA)资源消耗更少, 运算速度更快, 与其他方法相比, 硬件资源消耗减少了52.9%, 标量乘法运算速度提高了5倍, 能更好地适用于资源受限设备的应用。

关键词: 标量乘法, 二进制域, 求逆, 椭圆曲线密码体制, 现场可编程门阵列

Abstract: In recent years, the communications field has achieved tremendous development.Applications such as online banking and mobile communications have increased the security requirements in resource-constrained environments.Compared with traditional cryptographic algorithms, elliptic curve cryptosystem(ECC) provides better security standards and more space for optimizing performance parameters.Therefore, an efficient elliptic curve cipher hardware design scheme is proposed.Based on the exis-ting research, the proposed scheme uses the projected coordinate system LD Montgomery ladder algorithm to study the core scalar multiplication operation in ECC, and uses parallel scheduling to reduce delay in the group operation layer.For finite field ope-rations, the bit-parallel multiplication algorithm and improved Euclidean inverse algorithm are adopted.Based on Xilinx Virtex-5 and Virtex-7 FPGA device, the architecture is implemented on the binary domains with lengths of 163, 233 and 283 respectively.The experimental results show that the proposed scheme requires less FPGA resource consumption and faster calculation speed.Compared with other methods, the hardware resource consumption is reduced by 52.9% and the scalar multiplication operation speed is increased by 3.7times, so it is better suitable for the application of resource-constrained devices.

Key words: Binary extension field, Elliptic curve cryptography, Field-programmable gate array, Inversion, Scalar multiplication

中图分类号: 

  • TP309
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