基于CORDIC算法的高精度浮点对称矩阵特征值分解的FPGA实现

计算机科学 ›› 2013, Vol. 40 ›› Issue (5): 35-37.

• 2012多值逻辑专栏 • 上一篇下一篇

基于CORDIC算法的高精度浮点对称矩阵特征值分解的FPGA实现

陈刚,陈旭,徐元,边昳,鲁华祥

中国科学院半导体研究所神经网络实验室北京100083;中国科学院半导体研究所神经网络实验室北京100083;中国科学院半导体研究所神经网络实验室北京100083;中国科学院半导体研究所神经网络实验室北京100083;中国科学院半导体研究所神经网络实验室北京100083

出版日期:2018-11-16 发布日期:2018-11-16
基金资助:
本文受国家自然科学基金(61076014),中科院战略性先导科技专项(XDA06020700)资助

Floating-point CORDIC-based Real-valued Symmetric Matrix Eigenvalue Decomposition on FPGA

CHEN Gang,CHEN Xu,XU Yuan,BIAN Yi and LU Hua-xiang

Online:2018-11-16 Published:2018-11-16

摘要/Abstract

摘要： 为了提高实对称矩阵特征值分解算法的速度,在FPGA上设计并实现了符合IEEE-754标准的单精度浮点(32-bit)CORDIC算法,以在保证运算精度的前提下,最大限度地优化资源和速度。整个设计是在Xilinx公司的Spartan-3xc3sd1800a-5FPGA上实现的。测试结果显示:1)对于3*3的实对称矩阵(每个矩阵元素是32-bit浮点数),精度达到2－20;2)设计实现的结构占用2467个 slices,占芯片总资源的14%,最高运行时钟频率达到154MHz。

关键词: 特征值分解,CORDIC,FPGA,浮点数据

Abstract: This paper presented the architecture of real-valued symmetric matrix eigenvalue decomposition based on rotation mode CORDIC algorithm on FPGA．The proposed architecture adopts a direct mapping by 32floating-point CORDIC-based process units that can compute the eigenvalue decomposition for a 3*3real symmetric matrix．In order to achieve a comprehensive resource and performance evaluation,the whole design was realized on Spartan-3xc3sd1800a-5FPGA．The evaluation results show that 1) the proposed architecture satisfies 3*3eigenvalue decomposition for the 2－20accuracy requirement when the word length of the data path is 32-bit; 2) occupies about 2467(14%) slices,and the maximum frequency is 154MHz．

Key words: Eigenvalue decomposition,CORDIC,FPGA,Floating data

陈刚,陈旭,徐元,边昳,鲁华祥. 基于CORDIC算法的高精度浮点对称矩阵特征值分解的FPGA实现[J]. 计算机科学, 2013, 40(5): 35-37. https://doi.org/

CHEN Gang,CHEN Xu,XU Yuan,BIAN Yi and LU Hua-xiang. Floating-point CORDIC-based Real-valued Symmetric Matrix Eigenvalue Decomposition on FPGA[J]. Computer Science, 2013, 40(5): 35-37. https://doi.org/

参考文献

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基于CORDIC算法的高精度浮点对称矩阵特征值分解的FPGA实现

Floating-point CORDIC-based Real-valued Symmetric Matrix Eigenvalue Decomposition on FPGA

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