Computer Science

Computer Science ›› 2021, Vol. 48 ›› Issue (6A): 608-612.doi: 10.11896/jsjkx.200800134

• Interdiscipline & Application • Previous Articles     Next Articles

LDPC Adaptive Minimum Sum Decoding Algorithm and Its FPGA Implementation

WANG Deng-tian1, ZHOU Hua1,2,3, QIAN He-yue1   

  1. 1 Nanjing University of Information Technology,Nanjing 210044,China
    2 Jiangsu Collaborative Innovation Center for Atmospheric Environment and Equipment Technology,Nanjing 210044,China
    3 Jiangsu Key Laboratory of Meteorological Observation and Information Processing,Nanjing 210044,China
  • Online:2021-06-10 Published:2021-06-17
  • About author:WANG Deng-tian,born in 1995,master.His main research interests include information theory and coding.
  • Supported by:
    General Project of the National Natural Science Foundation of China(61771248).

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Abstract: The belief propagation(BP) decoding algorithm for low-density parity-check (LDPC) codes has been shown to approach the Shannon limit,however it requires extremely complex logarithmic and trigonometric functions,which is not of practical interest.The minimum sum (MS) algorithm improves the convenience speed and simplifies the calculation at the expense of loss in decoding performance.In order to reduce the loss in bit error rate (BER),this paper introduce an adaptive multiplicative factor which considers the relationship between the absolute value of the input variable node side information,the second smallest value and the hyperbolic tangent function.As a result,the performance of the proposed adaptive MS algorithm is 0.2dB superior to the traditional LLR (Log-Likelihood Ratio) BP algorithm.Also,LDPC codes of 155 lengths are implemented based on the Xilinx FPGA platform.

Key words: Adaptive minimum sum algorithm, Adaptive multiplicative factor, Algorithm performance, FPGA implementation, LDPC code

CLC Number: 

  • TN919.3
[1] 王琼,李思舫,罗亚洁.LDPC码的自适应补偿最小和译码算法[J].电讯术,2019,59(6):635-640.
[2] 杨卫国.基于减少过估计的改进LDPC码最小和译码算法[J].指挥控制与仿真,2017,39(6):53-57.
[3] GALLAGER R.Low-density parity-check codes[J].journal of circuits & systems,2008,8(1):3-26.
[4] 张玉凯.准循环LDPC码的编译码器设计及FPGA实现[D].西安:西安电子科技大学,2009.
[5] CHEN J H,DHOLAKIA A,ELEFTHERIOU E.Reduced-Complexity Decoding of LDPC Codes[J].Communications IEEE Transactions on,2005,53(8):1288-1299.
[6] ANGARITA F,VALLS J,ALMENAR V,et al.Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor[J].Circuits and Systems I:Regular Papers,IEEE Transactions on,2014,61(7):2150-2158.
[7] 姜莹.基于FPGA的高效LDPC译码器的研究[D].北京:北京交通大学,2014.
[8] 韩家宇.基于FPGA的LDPC码编译码研究及硬件实现[D].哈尔滨:哈尔滨工程大学,2017.
[9] VITYAZEVV V,LIKHOBABIN E A,USTINOVA E A.Min-sum algorithm-structure based decoding algorithms for LDPC codes[C]//2014 3rd Mediterranean Conference on Embedded Computing(EMCO).2014:256-259.
[10] 马志刚,郑鹏宇,王亚军.QC-LDPC译码器的FPGA设计实现与分析[J].现代导航,2017,8(3):204-209.
[11] 袁瑞佳.LDPC码的高效编译码实现技术研究[D].西安:西安电子科技大学,2012.
[12] LI H,DING H,ZHENG L,et al.An efficient scheduling scheme for layered belief propagation decoding of regular LDPC codes[C]//International Conference on Ultra Modern Telecommunications.2016:397-400.
[13] 黄福威.5G-LDPC码编译码器设计与FPGA实现技术研究[D].西安:西安电子科技大学,2019.
[14] 张辉.基于FPGA的LDPC译码器硬件实现方法研究[D].哈尔滨:哈尔滨工业大学,2019.
[15] 李硕.基于FPGA的QC-LDPC编译码器研究[D].哈尔滨:哈尔滨理工大学,2015.
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